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1 features ? avr ? microcontroller-based function controller fully programmable usb low-/full-speed function with five endpoints high performance and low power 1.5/ 12/24 mips avr risc microcontroller 120 powerful instructions ? most wi th 83 ns execution cycle times 24 kb masked rom program memory 1 kb internal sram 32 x 8 general-purpose working registers 19 programmable i/o port pins 12 channels 10-bit a-to-d converter programmable spi serial interface one 8-bit timer counter wi th separate pre-scaler one 16-bit timer counter with se parate pre-scaler and two pwms external and intern al interrupt sources programmable watchdog timer low power idle and power-down modes 6 mhz crystal oscillator with pll 5v operation with on-c hip 3.3v regulators 48-lead lqfp package binary compatible with the at43usb355 description the atmel at43usb351m is a usb avr-based microcontroller that is configurable as a low-speed or full-speed usb device. its program memory is a 24-kbyte mask pro- grammable rom and its data memory is 1-kbyte sram. the on-chip peripherals consists of 19 general-purpose i/o ports, two timer-counters, spi serial interface, a pwm and a 10-bit ad converter with 12 input channels. the mcu of the at43usb351m is a high performance 8-bit avr risc that operates at a clock frequency of 1.5 mhz, 12 mhz or 24 mhz. the a-to-d converter has a min- imum conversion time of 12 s that together with the 12 input channel should cover even the most demanding game controllers such as gamepads, joysticks and racing wheels. the two pwm outputs can be programmed for 8-, 9- or 10-bit resolution for applications requiring force feedback. the 19 general-purpose programmable i/o pins provide generous inputs for the various bu ttons and switches and led indicators that are being used in increasing numbers in today's game controllers. the usb function has one control endpoi nt and four additional programmable end- points, each with their own fifos. two of the endpoints have a 64-byte fifo each, while the other two have 8-byte fifos. the usb hardware supports the physical and link layers of the usb protocol while the transaction layer function must be imple- mented in the mcu's firmware. the avr architecture was developed to be programmed in c efficiently and without loss in performance. the at43usb351m is binary-compatible with the at43usb355. program develop- ment and debugging for the at43usb351m uses the at43dk355 and all its tools and libraries. full-speed/ low-speed usb microcontroller with adc and pwm at43usb351m rev. 3302e?usb?7/04
2 at43usb351m 3302e?usb?7/04 pin configuration figure 1. at43usb351m 48-lead lqfp figure 2. low-/full-speed usb microcontroller with adc and pwm 2xn vssa cexta vcca adc0 adc1 adc2 adc3 adc4 adc5 adc6 adc7 adc8 adc9 adc10 adc11 test resetn pa0 pa1 pa2 pa3 pa4 pa5 cext2 vcc2 vss2 pd6 pd5 xtal1 xtal2 lft pd4 pd3 pd2 pd1 pd0 dm vcc1 cext1 vss1 pb7 pb6 pb5 pb4 pa7 pa6 dp 1 25 AT43USB351M-AC 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 usb gpio osc + pll adc avr timer/ counter spi voltage regulators rom & sram pa[0:7] pb[4:7] pd[0:6] adc[0:11] vcc[1,2,a] vss[1,2,a] cext[1,2,a] dp0 dm0 xtal1 xtal2 lft rstn test
3 at43usb351m 3302e?usb?7/04 pin assignment pin# signal type pin# signal type 1 pd0 bi-directional 25 adc7 input 2 dp bi-directional 26 adc6 input 3 dm bi-directional 27 adc5 input 4 cext1 power supply/ground 28 adc4 input 5 vcc1 power supply/ground 29 adc3 input 6 vss1 power supply/ground 30 adc2 input 7 pb7 bi-directional 31 adc1 input 8 pb6 bi-directional 32 adc0 input 9 pb5 bi-directional 33 vcca power supply/ground 10 pb4 bi-directional 34 cexta power supply/ground 11 pa7 bi-directional 35 vssa power supply/ground 12 pa6 bi-directional 36 2xn input 13 pa5 bi-directional 37 cext2 power supply/ground 14 pa4 bi-directional 38 vcc2 power supply/ground 15 pa3 bi-directional 39 vss2 power supply/ground 16 pa2 bi-directional 40 pd6 bi-directional 17 pa1 bi-directional 41 pd5 bi-directional 18 pa0 bi-directional 42 xtal1 input 19 resetn input 43 xtal2 output 20 test input 44 lft output 21 adc11 input 45 pd4 bi-directional 22 adc10 input 46 pd3 bi-directional 23 adc9 input 47 pd2 bi-directional 24 adc8 input 48 pd1 bi-directional
4 at43usb351m 3302e?usb?7/04 signal description name type function v cc1 , 2 power supply/ground 5v digital power supply v cca power supply/ground 5v power supply for the adc v ss1 , 2 power supply/ground digital ground v ssa power supply/ground ground for the adc cext1, 2 power supply/ground external capacitors for power supplies ? high quality 2.2 f capacitors must be connected to cext1 and cext2 for proper operation of the chip. cexta power supply/ground external capacitor for analog power supply ? a high quality 0.33 f capacitor must be connected to cexta for proper operation of the chip. xtal1 input oscillator input ? input to the inverting oscillator amplifier. xtal2 output oscillator output ? output of the inverting oscillator amplifier. lft input pll filter ? for proper operation of the pll, this pin should be connected through a 0.01 f capacitor in parallel with a 100 ? resistor in series with a 0.1 f capacitor to ground (vss). both capacitors must be high quality ceramic. dpo bi-directional upstream plus usb i/o ? this pin should be connected to cext1 through an external 1.5 k ? . dmo bi-directional upstream minus usb i/o pa[0:7] bi-directional port a[0:7] ? bi-directional 8-bit i/o port with 2 ma drive strength and a programmable pull-up resistor. pb[4:7] bi-directional port b[4:7] ? bi-directional 8-bit i/o port with 2 ma drive strength and a programmable pull-up resistor. pb[4:7] have dual functions as shown below: port pin alternate function pb4 ssn, spi slave port select or scl, i2c serial bus clock pb5 mosi, spi slave port select input pb6 miso, spi master data in, slave data out pb7 sck, spi master clock out, slave clock in pd[0:6] bi-directional port d[0:6] ? bi-directional i/o ports with 2 ma drive strength and a programmable pull-up resistor. portd[2:6] have dual functions as shown below: port pin alternate function pd2 int0, external interrupt 0 pd3 int1, external interrupt 1 pd4 icp, timer/counter, input capture pd5 oc1a timer/counter1 output compare a pd6 oc1b timer/counter1 output compare b adc[0:11] input adc input[0:11] ? 12-bit input pins for the adc. test input test pin ? this pin should be tied to ground. resetn input reset ? active low. 2xn input clock frequency selector (table 1 on page 6)
5 at43usb351m 3302e?usb?7/04 figure 3. the at43usb351m enhanced risc architecture interrupt unit 8-bit timer/counter 16-bit timer/counter watchdog timer spi unit adc status and control program counter 12k x 16 program memory instruction register instruction decoder control lines 32 x 8 general-purpose registers alu 1024 x 8 sram 19 gpio lines usb function
6 at43usb351m 3302e?usb?7/04 architectural overview the at43usb351m is binary-compatible wit h the at43usb355 compound device. firmware developed for the at43usb355 will run on the at43usb351m. the peripherals and features of the at43usb351 m microcontroller are similar to those of the at90s8515, with the exception of the following modifications: no eeprom no external data memory accesses no uart idle mode not supported usb function on-chip adc the embedded usb hardware of the at43usb351m is a usb function with an 8-byte control endpoint and four additional programmable endpoints with separate fifos. two of the fifos are 64 bytes deep and the other two are 8 bytes deep. depending on the usb speed and the state of 2xn input signal, device pin 36, the mcu runs at 1.5 mhz, 12 mhz or 24 mhz. the clock that operates the mcu is generated by the usb hardware. while at 12 mhz, the nominal and average period of the clock is 83.3 ns, it may have single cycles that deviate by 20.8 ns during a phase adjustment by the sie?s clock/data separator of the usb hardware. similarly at 1. 5 mhz, the mcu clock runs 8 times slower and at 24 mhz, two times faster than the 12 mhz mode. the clock frequencies of the various mod- ules of the at43usb351m is summarized in the following table: the microcontroller shares most of the control and status registers of the megaavr microcon- troller family. the registers for managing the usb operations are mapped into its sram space. the i/o section on page 15 summarizes the available i/o registers. the ?avr register set? on page 36 covers the avr registers. please refer to the atmel avr manual for more information. the fast-access register file concept contai ns 32 x 8-bit general-purpose working registers with a single clock cycle access ti me. this means that during on e single clock cycle, one arith- metic logic unit (alu) operation is executed. tw o operands are output from the register file, the operation is executed, and the result is stored back in the register file ? in one clock cycle. six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing - enabling efficient address calculations. one of the three address pointers is also used as the address pointer for look-u p tables in program memory. these added func- tion registers are the 16-bit x-, y- and z-registers. the alu supports arithmetic and logic operations between registers or between a constant and a register. single register operations are also executed in the alu. figure 3 on page 5 shows the at43usb351m avr enhanced risc microcontroller architecture. in addition to the register operation, the conventional memory addressing modes can be used on the register file as well. this is enabled by the fact that the register file is assigned the 32 table 1. clock frequencies usb mode 2xn pin mcu clock timer/counter clock adc clock spi clock wdt clock full speed 0 24 mhz 12 mhz 1 mhz 24 mhz 1 mhz full speed 1 12 mhz 12 mhz 1 mhz 12 mhz 1 mhz low speed 0 24 mhz 12 mhz 1 mhz 24 mhz 1 mhz low speed 1 1.5 mhz 1.5 mhz 1 mhz 1.5 mhz 1 mhz
7 at43usb351m 3302e?usb?7/04 lowest data space addresses ($00 - $1 f), allowing them to be accessed as though they were ordinary memory locations. the i/o memory space contains 64 addresses for cpu peripheral functions as control regis- ters, timer/counters, and other i/o functions. the i/o memory can be accessed directly, or as the data space locations following those of the register file, $20 - $5f. the avr uses a harvard architecture concept ? with separate memories and buses for pro- gram and data. the program memory is executed with a single-level pipelining. while one instruction is being executed, the next instruction is pre-fetched from the program memory. this concept enables instructions to be execut ed in every clock cycle. the program memory is a downloadable sram or a mask programmed rom. with the relative jump and call instructions, th e whole 24k address space is directly accessed. most avr instructions have a single 16-bit word format. every program memory address con- tains a 16- or 32-bit instruction. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is effectively allocated in the general data sram, and consequently, the stack size is only limited by the total sram size and the usage of the sram. all user pro- grams must initialize the stack pointer (sp) in the reset routine (before subroutines or interrupts are executed). the 10-bit sp is read/write accessible in the i/o space. the 1-kbyte data sram can be easily accessed through the five different addressing modes supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. a flexi- ble interrupt module has its control registers in the i/o space with an additional global interrupt enable bit in the status register. all interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program memory. the interrupts have priority in accor- dance with their interrupt vector position. the lower the interrupt vector address, the higher the priority. development support the at43usb351m uses the same program an d development tools as the at43usb355 and other atmel avr microcontrolle rs, including: c compilers, ma cro assemblers, program debug- gers/simulators and in-circuit emulators. the at43dk355 development kit is also available, including firmware sour ce code for the most common usb applications.
8 at43usb351m 3302e?usb?7/04 the general- purpose register file all register operating instructions in the inst ruction set have direct and single cycle access to all registers. the only exception is the five c onstant arithmetic and logic instructions sbci, subi, cpi, andi, and ori between a constant and a register, and the ldi instruction for load immediate constant data. these instructions apply to the second half of the registers in the register file ? r16..r31. the general sbc, sub, cp, and, and or and all other operations between two registers or on a single register apply to the entire register file. as shown in table 2, each register is al so assigned a data memory address, mapping them directly into the first 32 locations of the user data space. although not being physically imple- mented as sram locations, this me mory organization pr ovides great flexibility in access of the registers, as the x-, y-, and z-registers can be set to index any register in the file. table 2. avr cpu general-purpose working register register address comment r0 $00 r1 $01 r2 $02 .. r13 $0d r14 $0e r15 $0f r16 $10 r17 $11 .. r26 $1a x-register low byte r27 $1b x-register high byte r28 $1c y-register low byte r29 $1d y-register high byte r30 $1e z-register low byte r31 $1f z-register high byte
9 at43usb351m 3302e?usb?7/04 x-, y- and z- registers registers r26..r31 contain some added function s to their general-purpose usage. these reg- isters are address pointers for indirect addressing of the data space. the three indirect address registers x, y, and z are defined as: in the different addressing modes these address registers have functions as fixed displace- ment, automatic increment and decrement (see the descriptions for the different instructions). alu ? arithmetic logic unit the high-performance avr alu operates in direct connection with all 32 general-purpose working registers. within a single clock cycle, alu operations between registers in the register file are executed. the alu operations are divided into three main categories ? arithmetic, log- ical and bit-functions. program memory the at43usb351m contains 24k bytes on-chip masked programmable rom for program storage. since all instructions are 16- or 32-bit words, the program memory is organized as 12k x 16. the at43usb351m program counter (pc) is 14 bits wide, thus addressing the 12,288 program memory addresses. constant tables can be allocated within t he entire program memory address space (see the lpm - load program memory instruction description). read sequence where the functions overlap, the at43us b351m and the at43usb355 are binary-compati- ble. firmware written for th e at43usb355 will work unaltere d on the at43usb351m as long as the functions are supported by the at43usb351m. the only functional difference between the two devices are: x-register 15 xh xl 0 7070 r27 ($1b) r26 ($1a) y-register 15 yh yl 0 7070 r29 ($1d) r28 ($1c) z-register 15 zh zl 0 7070 r30 ($1f) r31 ($1e) function at43usb355 at43usb351 usb hub hub3 downstream ports and atta ched function function only, no hub port b pb[0:7] pb[4:7] port d pd[0:7] pd[0:6] port f pf[0:3} no port f
10 at43usb351m 3302e?usb?7/04 sram data memory table 4 summarizes how the at43usb351m sram memory is organized. the lower 1120 data memory locations address the register file, the i/o memory and the internal data sram. the first 96 locations address the register file + i/o memory, and the next 1024 locations address the internal data sram. the five di fferent addressing modes for the data memory cover: direct, indirect with displacement, indi rect, indirect with pre-decrement and indirect with post-increment. in the register file, registers r26 to r31 feature the indirect addressing pointer registers. direct addressing reaches the entire data space. the indirect with displacement mode features 63 address locations that reach from the base address given by the y- or z-register. when using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers x, y, and z are decremented and incremented. the 32 general-purpose working registers, 64 i/o registers and the 1024 bytes of internal data sram in the at43usb351m are all accessible through these addressing modes. to manage the usb hardware, a special set of registers is assigned. these registers are mapped to sram space between addresses $1f00 and 1fff. table 4 and table 5 give an overview of these registers.
11 at43usb351m 3302e?usb?7/04 table 3. sram organization register file data address space r0 $0000 r1 $0001 r30 $001e r31 $001f i/o registers $00 $0020 $01 $0021 $3e $005e $3f $005f internal sram $0060 $0061 $025e $045f usb registers $1f00 $1ffe $1fff
12 at43usb351m 3302e?usb?7/04 table 4. usb hub and function registers address name function $1ffd frm_num_h frame number high register $1ffc frm_num_l frame number low register $1ffb glb_state global state register $1ffa sprsr suspend/resume register $1ff9 sprsie suspend/resume interrupt enable register $1ff8 sprsmsk suspend/resume interrupt mask register $1ff7 uisr usb interrupt status register $1ff6 uimskr usb interrupt mask register $1ff5 uiar usb interrupt acknowledge register $1ff3 uier usb interrupt enable register $1fef haddr hub address register $1fee faddr function address register $1fe6 fendp4_cntr function endpoint 4 control register $1fe5 fendp0_cntr function endpoint 0 control register $1fe4 fendp1_cntr function endpoint 1 control register $1fe3 fendp2_cntr function endpoint 2 control register $1fe2 fendp3_cntr function endpoint 3 control register $1fde fcsr4 function controller endpoint 4 service routine register $1fdd fcsr0 function controller endpoint 0 service routine register $1fdc fcsr1 function controller endpoint 1 service routine register $1fdb fcsr2 function controller endpoint 2 service routine register $1fda fcsr3 function controller endpoint 3 service routine register $1fd6 fdr4 function enbpoint 4 fifo data register $1fd5 fdr0 function endpoint 0 fifo data register $1fd4 fdr1 function endpoint 1 fifo data register $1fd3 fdr2 function endpoint 2 fifo data register $1fd2 fdr3 function endpoint 3 fifo data register $1fce fbyte_cnt4 function endpoint 4 byte count register $1fcd fbyte_cnt0 function endpoint 0 byte count register $1fcc fbyte_cnt1 function endpoint 1 byte count register $1fcb fbyte_cnt2 function endpoint 2 byte count register $1fca fbyte_cnt3 function endpoint 3 byte count register $1fa6 fcar4 function endpoint 4 control and acknowledge register $1fa5 fcar0 function endpoint 0 control and acknowledge register $1fa4 fcar1 function endpoint 1 control and acknowledge register $1fa3 fcar2 function endpoint 2 control and acknowledge register $1fa2 fcar3 function endpoint 3 control and acknowledge register
13 at43usb351m 3302e?usb?7/04 table 5. usb hub and function registers name address bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 bit 1 bit 0 glb_state $1ffb ? susp flg resume flg rmwupe confg hadd en sprsr $1ffa ? ? ? ? ? frwup rsm glb susp sprsie $1ff9 ? ? ? ? ? frwup ie rsm ie glb susp ie sprsmsk $1ff8 ? ? ? ? ? frwup msk rsm msk glb susp msk uisr $1ff7 sof int eof2 int ? fep4 int f ep3 int fep2 int fep1 int fep0 int uimskr $1ff6 sof msk sof2 msk ? fep3 msk hep0 msk fep2 msk fep1 msk fep0 msk uiar $1ff5 sof intack eof2 intack ? fep3 intack hep0 intack fep2 intack fep1 intack fep0 intack uier $1ff3 sof ie eof2 ie ? fep3 ie hep0 ie fep2 ie fep1 ie fep0 ie uovcer $1ff2 ? ? ? ? ? port2 ? ? haddr $1fef saen hadd6 hadd5 hadd4 hadd3 hadd2 hadd1 hadd0 faddr $1fee fen fadd6 fadd5 fadd4 fadd3 fadd2 fadd1 fadd0 fendp4_cntr $1fe6 epen ? ? ? dtgle epdir eptype1 eptype0 fendp0_cntr $1fe5 epen ? ? ? dtgle epdir eptype1 eptype0 fendp1_cntr $1fe4 epen ? ? ? dtgle epdir eptype1 eptype0 fendp2_cntr $1fe3 epen ? ? ? dtgle epdir eptype1 eptype0 fendp3_cntr $1fe2 epen ? ? ? dtgle epdir eptype1 eptype0 fcsr4 $1fde ? ? ? ? stall sent ? rx out packet tx cemplete fcsr0 $1fdd ? ? ? ? stall sent rx setup rx out packet tx complete fcsr1 $1fdc ? ? ? ? stall sent ? rx out packet tx complete fcsr2 $1fdb ? ? ? ? stall sent ? rx out packet tx complete fcsr3 $1fda ? ? ? ? stall sent ? rx out packet tx complete hdr4 $1fd6 data7 data6 data5 data4 data3 data2 data1 data0 fdr0 $1fd5 data7 data6 data5 data4 data3 data2 data1 data0 fdr1 $1fd4 data7 data6 data5 data4 data3 data2 data1 data0 fdr2 $1fd3 data7 data6 data5 data4 data3 data2 data1 data0 fdr3 $1fd2 data7 data6 data5 data4 data3 data2 data1 data0 fbyte_cnt4 $1fce ? ? bytct5 bytct 4 bytct3 bytct2 bytct1 bytct0 fbyte_cnt0 $1fcd ? ? bytct5 bytct 4 bytct3 bytct2 bytct1 bytct0 fbyte_cnt1 $1fcc ? bytct6 bytct5 bytct4 bytct3 bytct2 bytct1 bytct0 fbyte_cnt2 $1fcb ? bytct6 bytct5 bytct4 bytct3 bytct2 bytct1 bytct0 fbyte_cnt3 $1fca ? ? bytct5 bytct 4 bytct3 bytct2 bytct1 bytct0 hstr $1fc7 ? ? ? ? ovlsc lpsc ovi lps hpcon $1fc5 ? hpcon2 hpcon1 hpcon0 ? hpadd2 hpadd1 hpadd0 hpstat3 $1fba ? lsp ppstat prstat poci psstat pestat pcstat hpstat2 $1fb9 ? lsp ppstat prstat poci psstat pestat pcstat hpstat1 $1fb8 ? lsp ppstat prstat poci psstat pestat pcstat hpscr3 $1fb2 ? ? ? rsts c pocic pssc pesc pcsc hpscr2 $1fb1 ? ? ? rsts c pocic pssc pesc pcsc hpscr1 $1fb0 ? ? ? rsts c pocic pssc pesc pcsc pstate3 $1faa ? ? ? ? ? ? dpstate dmstate pstate2 $1fa9 ? ? ? ? ? ? dpstate dmstate fcar4 $1fa6 ctl dir data end force stall tx packet re ady stall_sent-ack ? rx_out_packet_ack tx_complete-ack
14 at43usb351m 3302e?usb?7/04 fcar0 $1fa5 ctl dir data end force stall tx packet ready sta ll_sent-ack rx_setup_ack rx_out_packet_ack tx_complete-ack fcar1 $1fa4 ctl dir data end force stall tx packet re ady stall_sent-ack ? rx_out_packet_ack tx_complete-ack fcar2 $1fa3 ctl dir data end force stall tx packet re ady stall_sent-ack ? rx_out_packet_ack tx_complete-ack fcar3 $1fa2 ctl dir data end force stall tx packet re ady stall_sent-ack ? rx_out_packet_ack tx_complete-ack table 5. usb hub and function registers (continued) name address bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 bit 1 bit 0
15 at43usb351m 3302e?usb?7/04 i/o memory the i/o space definition of the at43usb351m is shown in the following table: table 6. i/o memory space i/o (sram) address name function $3f ($5f) sreg status register $3e ($5e) sph stack pointer high $3d ($5d) spl stack pointer low $3b ($5b) gimsk general interrupt mask register $3a ($5a) gifr general interrupt flag register $39 ($59) timsk timer/counter interrupt mask register $38 ($58) tifr timer/counter interrupt mask register $35 ($55) mcucr mcu general control register $33 ($53) tccr0 timer/counter0 control register $32 ($52) tcnt0 timer/counter0 (8 bit) $2f ($4f) tccr1a timer/counter1 control register a $2e ($4e) ttcr1b timer/counter0 control register b $2d ($52) tcnt1h timer/counter1 high byte $2c ($52) tcnt1l timer/counter0 low byte $2b ($4b) ocr1ah timer/counter1 output compare register a high byte $2a ($4a) ocr1al timer/counter1 output compare register a low byte $29 ($49) ocr1bh timer/counter1 output compare register b high byte $28 ($48) ocr1bl timer/counter1 output compare register b low byte $25 ($45) icr1h t/c 1 input capture register high byte $24 ($44) icr1l t/c 1 input capture register low byte $21 ($41) wdtcr watchdog timer counter register $1b ($4b) porta data register, port a $1a ($3a) ddra data direction register, port a $19 ($39) pina input pins, port a $18 ($38) portb data register, port b $17 ($37) ddrb data direction register, port b $16 ($36) pinb input pins, port b $12 ($32) portd data register, port d $11 ($31) ddrd data direction register, port d $10 ($30) pind input pins, port d $0f ($2f) spdr spi i/o data register $0e ($2e) spsr spi status register $0d ($2d) spcr spi control register $08 ($28) admux adc mux select register
16 at43usb351m 3302e?usb?7/04 all at43usb351m i/o and peripherals, except fo r the usb hardware registers, are placed in the i/o space. the i/o locations are accessed by the in and out instructions transferring data between the 32 general-purpose working registers and the i/o space. i/o registers within the address range $00 ? $1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instruc- tions. refer to the instruction set documentations of the avr for more details. when using the i/o specific commands, in and out, the i/o address $00 ? $3f must be used. when address- ing i/o registers as sram, $20 must be added to this address. all i/o register addresses throughout this document are shown with the sram address in parentheses. for compatibility with future devi ces, reserved bits should be wr itten to zero if accessed. reserved i/o memory addresses should never be written. usb function a unique feature of the at43usb351m is that its usb function can operate as a full-speed or low-speed usb device. the at43usb351m?s usb hardware detects where the 1.5 k ? pull-up resistor is connected, i.e. dp or dm, and selects the correct mode automatically. if the pull-up resistor is connected to dp, full-speed mode is entered and if dm, low-speed mode is entered. firmware for low-speed and full-speed, and vice versa, may not work interchangeably. among other things, usb bus signaling interrupts are different for the two modes. for example, in the full-speed mode, an interrupt can be generated at sof. this is not available in the low-speed mode. table 1 in the ?architectural overview? sect ion describes the effect of usb speed and mcu frequency speed selection on the various clock frequencies of the peripheral modules of the at43usb351m. the embedded usb function has a default endpoint plus 4 other programmable endpoints. two of these endpoints contain their own 64-by te fifo, while the other two have 8-byte fifos. endpoints 1 - 4 can be programmed as interrupt in or out or bulk in or out end- points. note that in the low-speed mode, the maximum data packet is 8 bytes and only interrupt in or out endpoints are allowed. $07 ($27) adcsr adc contro l and status register $03 ($23) adch adc high byte data register $02 ($22) adcl adc low byte data register table 6. i/o memory space (continued) i/o (sram) address name function
17 at43usb351m 3302e?usb?7/04 figure 4. usb hardware hub repeater full-speed/low-speed serial interface engine avr microcontroller data address control function interface unit usb xcvr
18 at43usb351m 3302e?usb?7/04 functional description on-chip power supply the at43usb351m contains three on-chip power supplies that generate 3.3v with a capacity of 30 ma each from the 5v power input. the on-chip power supplies are intended to supply the at43usb351m internal circuit and the 1.5k pull-up resistor only and should not be used for other purposes. external 2.2 f filter capacitors are required at the power supply outputs, cext1 and cext2 and 0.33 fal cexta. the internal power supplies can be disabled as described in the next paragraph. the user should be careful when the gpio pins are required to supply high-load currents. if the application requires that the gpio supply currents beyond the capability of the on-chip power supply, the at43usb351m should be supplied by an external 3.3v power supply. in this case, the 5v v cc power supply pin should be left unconnected and the external 3.3v power supplied to the chip through the cext1, cext2 and cexta pins. i/o pin characteristics the i/o pins of the at43usb351m should not be directly connected to voltages less than v ss or more than the voltage at the voltage regulator pins. if it is necessary to violate this rule, insert a series resistor between the i/o pin and the source of the external signal source that limits the current into the i/o pin to less than 2 ma. under no circumstance should the external voltage exceed 5.5v. to do so will put the chip under excessive stress. oscillator and pll all clock signals required to operate the at43us b351m are derived from an on-chip oscillator and a 6 mhz crystal or resonator (low-speed only). in full-speed mode, an on-chip pll gener- ates the high frequency for the clock/data separator of the serial interface engine. in the suspended state, the oscillator ci rcuitry is turned off. in low- speed mode, the pll is disabled. the oscillator of the at43usb351 m is a special, low-drive type , designed to work with most crystals without any external components. the crystal must be of the parallel resonance type requiring a load capacitance of about 10 pf. if the crystal requires a higher value capacitance, external capacitors can be added to the two termi nals of the crystal and ground to meet the required value. to assure quick start-up, a crystal with a high q, or low esr, should be used. if the at43usb351m is to operate in full-speed usb mode, the crystal should have an accu- racy and stability of better than 100 ppm. the use of a cerami c resonator in place of the crystal is not recommended for full-speed usb, because a resonator would not have the nec- essary frequency ac curacy and stability. the clock can also be externally sourced. in th is case, connect the clock source to the xtal1 pin, while leaving xtal2 pin fl oating. the switching level at the osc1 pin can be as low as 0.47v and a cmos device is required to drive this pin to maintain good noise margins at the low switching level. for proper operation of the pll, an external rc filter consisting of a series rc network of 100 ? and 0.1 f in parallel with a 0.01 f capacitor must be connected from the lft pin to v ss . use only high-quality ceramic capacitors.
19 at43usb351m 3302e?usb?7/04 figure 5. oscillator and pll reset and interrupt handling the at43usb351m provides 20 different interrupt sources with 11 separate reset vectors, each with a separate program vector in the program memory space. eleven of the interrupt sources share 2 interrupt reset vectors. these 11 are the usb related interrupts. all interrupts are assigned individual enable bits which must be set (one) together with the i-bit in the status register in order to enable the interrupt. the lowest addresses in the program memory space are automatically defined as the reset and interrupt vectors. the complete list of vectors is shown in table 7. the list also determines the priority levels of the different interrupts. the lower the address, the higher is the priority level. reset has the highest pr iority, and next is int0 ? th e usb suspend and resume inter- rupt, etc. at43usb351m xtal1 xtal2 lft y1 6.000 mhz u1 c2 0.01 uf c1 0.22 uf r1 100 table 7. reset and interrupt vectors vector no. program address source interrupt definition 1 $000 reset external reset, power-on reset and watchdog reset 2 $002 int0 usb suspend and resume 3 $004 int1 external interrupt request 1 4 $006 timer1 capt timer/counter1 capture event 5 $008 timer1 compa timer/counter1 compare match a 6 $00a timer1 compb timer/counter1 compare match b 7 $00c timer1, ovf timer/counter1 overflow 8 $00e timer0, ovf timer/counter0 overflow 9 $010 spi, stc spi serial transfer complete 12 $016 adc adc conversion complete 13 $018 usb hw usb hardware
20 at43usb351m 3302e?usb?7/04 the most typical and general program setup for the reset and interrupt vector addresses are: usb related interrupt events are routed to reset vectors 13 and 2 through a separate set of interrupt, interrupt enable and interrupt mask registers that are mapped to the data sram space. these interrupts must be enabled though their control register bits. in the event an interrupt is generated, the source of the interrupt is identified by reading the interrupt registers. the usb frame and transaction related interrupt events, such as start of frame interrupt, are grouped in one set of registers: usb interrupt flag register, usb interrupt enable register and usb interrupt mask register. the usb bus reset and suspend/resume are grouped in another set of registers: suspend/resume r egister, suspend/resume interrupt enable reg- ister and suspend/resume interrupt mask register. address labels code comments $000 jmp reset ; reset handler $004 jmp ext_int1 ; irq1 handler $00e jmp tim0_ovf ; timer0 overflow handler $018 jmp usb_hw ; usb handler ; $00d main: ldi r16, high (ramend) ; main program start $00e out sph, r16 $00f ldi r16, low (ramend) $010 out spl, r16 $011 xxx ... ... ... ...
21 at43usb351m 3302e?usb?7/04 figure 6. at43usb351m interrupt structure reset sources the at43usb351m has fo ur sources of reset: power-on reset ? the mcu is reset when the supply voltage is below the power-on reset threshold. external reset ? the mcu is reset when a low leve l is present on the resetn pin for more than 50 ns. watchdog reset ? the mcu is reset when the watchdog timer period expires and the watchdog is enabled. usb reset ? the at43usb351m has a feature to separate the usb and microcontroller resets. this feature is enabled by setting the bus int en, bit 3 of the sprsie register. a usb bus reset is defined as a se0 (single ende d zero) of at least 4 slow speed usb clock cycles received by port0. the internal reset pulse to the usb hardware and microcontroller lasts fo r 24 oscillator periods. ? resets not separated: a usb bus rese t will also reset the microcontroller. ? separated reset: a usb bus reset will onl y reset the usb hardware, while an interrupt to the microcontr oller will be generated if the bus int msk bit, bit 3 of sprsmsk register, is also set. suspend/resume register suspend/resume interrupt enable register suspend/resume interrupt mask register usb interrupt flag register usb interrupt enable register usb interrupt mask register usb adc spi stc timer0 ovf timer1 ovf timer1 compb timer1 compa timer1capt int1 int0 reset microcontroller interrupt logic 13 12 9 8 7 6 5 4 3 2 1 sof fep4 fep3 fep2 fep1 fep0 reserved reserved frmwup rsm glb susp bus reset
22 at43usb351m 3302e?usb?7/04 when the usb hardware is reset, the usb device is de-configured and has to be re-enumer- ated by the host. when the microcontroller is reset, all i/o registers are then set to their initial values, and the program starts execution from address $000. the instruction placed in address $000 must be a jmp instruction to the reset handling routine. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. the circuit diagram in figure 7 shows the reset logic. figure 7. reset logic power-on reset a power-on reset (por) circuit ensures that t he device is reset from power-on. an internal timer clocked from the watchdog timer oscillator prevents the mcu from starting until after a certain period after v cc has reached the power-on threshold voltage, regardless of the v cc rise time. if the build-in start-up delay is suffi cient, reset can be connected to v cc directly or via an external pull-up resistor. by holding the pin low for a period after v cc has been applied, the power-on reset period can be extended. fstrt cntr reset usb reset or por ckt reset ckt watchdog timer divider 14-bit cntr vcc rstn 1 mhz clock s r on
23 at43usb351m 3302e?usb?7/04 external reset an external reset is generated by a low-level on the reset pin. reset pulses longer than 200 ns will generate a reset. sh orter pulses are not guaranteed to generate a reset. when the applied signal reaches the reset threshold voltage - v rst on its positive edge, the delay timer starts the mcu after the time-out period t tout has expired. figure 8. external reset during operation watchdog timer reset when the watchdog time s out, it will generate a short reset pu lse of 1 xtal cycle duration. on the falling edge of this pulse, the delay timer starts counting the time-out period t tout . figure 9. watchdog reset during operation non-usb related interrupt handling the at43usb351m has two non-usb 8-bit interrupt mask control registers; gimsk (general interrupt mask register) and timsk (timer/counter interrupt mask register). when an interrupt occurs, the global interrupt enable i-bit is cleared (zero) and all interrupts are disabled. the user software can set (one) the i-bit to enable nested interrupts. the i-bit is set (one) when a return from interrupt instruction, reti, is executed. for interrupts triggered by events that can remain static (e.g. the output compare register1 matching the value of timer/counter1) the inte rrupt flag is set when the event occurs. if the interrupt flag is cleared and the interrupt condition persists, the flag will not be set until the event occurs the next time. when the program counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, hard-ware clears the corresponding flag that generated the inter- rupt. some of the interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. t tout v rst vcc reset time-out internal reset t tout vcc reset wdt time-out reset time-out 1 xtal cycle internal reset
24 at43usb351m 3302e?usb?7/04 if an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set an d remembered until the interrup t is enabled, or the flag is cleared by software. if one or more interrupt conditions occur when the global interrupt enable bit is cleared (zero), the corresponding interrupt flag (s) will be set and remembered unt il the global interrupt enable bit is set (one), and will be exec uted by order of priority. note that external level interr upt does not have a flag, and will only be remembered for as long as the interrupt condition is active.
25 at43usb351m 3302e?usb?7/04 general interrupt mask register ? gimsk bit 7 ? int1: external interrupt request 1 enable when the int1 bit is set (one) and the i-bit in the status register (sreg) is set (one), the external pin interrupt is enabled. the interrupt sense control1 bits 1/0 (isc11 and isc10) in the mcu general control register (mcucr) define s whether the external interrupt is acti- vated on rising or falling edge of the int1 pi n or level sensed. activi ty on the pin will cause an interrupt request even if int1 is configured as an output. the corresponding interrupt of exter- nal interrupt request 1 is executed from program memory address $004. see also ?external interrupts? on page 28. bit 6 ? int0: interrupt request 0 (suspend/resume interrupt) enable when the int0 bit is set (one) and the i-bit in the status register (sreg) is set (one), the external pin interrupt is enabled. the interrupt sense control0 bits 1/0 (isc01 and isc00) in the mcu general control register (mcucr) define s whether the external interrupt is acti- vated on rising or falling edge of the int0 pi n or level sensed. activi ty on the pin will cause an interrupt request even if int0 is configured as an output. the corresponding interrupt of inter- rupt request 0 is executed from program memory address $002. see also ?external interrupts? on page 28. bits 5..0 ? res: reserved bits these bits are reserved bits in the at43usb351m and always read as zero. general interrupt flag register ? gifr bit 7 ? intf1: external interrupt flag1 when an event on the int1 pin triggers an interrupt request, intf1 becomes set (one). if the i-bit in sreg and the int1 bit in gimsk are se t (one), the mcu will jump to the in terrupt vec- tor at address $004. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. bit 6 ? intf0: interrupt flag0 (suspend/resume interrupt flag) when an event on the int0 (that is, a usb event-related interrupt) triggers an interrupt request, intf0 becomes set (one). if the i-bit in sreg and the int0 bit in gimsk are set (one), the mcu will jump to the in terrupt vector at address $002. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. bits 5..0 ? res: reserved bits these bits are reserved bits in the at43usb351m and always read as zero. bit 7 6 5 4 3 210 $3b ($5b) int1 int0 ? ? ? ? ? ? gimsk read/write r/w r/w r r r r r r initial value 0 0 0 0 0 0 0 0 bit 7 6 543210 $3a ($5a) intf1 int f0 ? ? ? ? ? ? gifr read/write r/w r/w r r r r r r initial value 0 0 0 0 0 0 0 0
26 at43usb351m 3302e?usb?7/04 timer/counter interrupt mask register ? timsk bit 7 ? toie1: timer/counter1 overflow interrupt enable when the toie1 bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 overflow interrupt is enabled. th e corresponding interrupt (at vector $006) is executed if an overflow in timer/counter1 occurs, i.e., when the tov1 bit is set in the timer/counter interrupt flag register (tifr). bit 6 ? oce1a: timer/counter1 output comparea match interrupt enable when the ocie1a bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 comparea match interrupt is enabled. the corresponding interrupt (at vector $004) is executed if a comparea match in timer/counter1 occurs, i.e., when the ocf1a bit is set in the tifr. bit 5 ? ocie1b: timer/counter1 output compareb match interrupt enable when the ocie1b bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 compareb match interrupt is enabled. the corresponding interrupt (at vector $005) is executed if a compareb match in timer/counter1 occurs, i.e., when the ocf1b bit is set in the tifr. bit 4 ? res: reserved bit this bit is a reserved bit in the at43usb351m and always reads zero. bit 3 ? ticie1: timer/counter1 input capture interrupt enable when the ticie1 bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 input capture event interrupt is enabled. the corresponding interrupt (at vec- tor $003) is executed if a capture-triggering event occurs on pin 45, icp, i.e., when the icf1 bit is set in the tifr. bit 2 ? res: reserved bit this bit is a reserved bit in the at43usb351m and always reads zero. bit 1 ? toie0: timer/counter0 overflow interrupt enable when the toie0 bit is set (one) and the i-bit in the status register is set (one), the timer/counter0 overflow interrupt is enabled. th e corresponding interrupt (at vector $007) is executed if an overflow in timer/counter0 occurs, i.e., when the tov0 bit is set in the tifr. bit 0 ? res: reserved bit this bit is a reserved bit in the at43usb351m and always reads zero. bit 7 6 5 4 3 210 $39 ($59) toie1 ocie1a ocie1nb ? ticie1 ? toie0 ? timsk read/write r/w r/w r/w r r/w r r/w r initial value 0 0 0 0 0 0 0 0
27 at43usb351m 3302e?usb?7/04 timer/counter interrupt flag register ? tifr bit 7 ? tov1: timer/counter1 overflow flag the tov1 is set (one) when an overflow occurs in timer/counter1. tov1 is cleared by the hardware when executing the corresponding interr upt handling vector. alternatively, tov1 is cleared by writing a logic one to the flag. when the i-bit in sreg, and toie1 (timer/counter1 overflow interrupt enable), and tov1 are set (one), the timer/counter1 overflow interrupt is executed. in pwm mode, this bit is set when timer/counter1 changes counting direction at $0000. bit 6 ? ocf1a: output compare flag 1a the ocf1a bit is set (one) when compare match occurs between the timer/counter1 and the data in ocr1a - output compare register 1a. ocf1a is cleared by the hardware when exe- cuting the corresponding interrupt handling vector. alternatively, ocf1a is cleared by writing a logic one to the flag. when the i-bit in sr eg, and ocie1a (timer/counter1 compare match interrupta enable), and the ocf1a are set (one), the timer/counter1 compare a match inter- rupt is executed. bit 5 ? ocf1b: output compare flag 1b the ocf1b bit is set (one) when compare match occurs between the timer/counter1 and the data in ocr1b - output compare register 1b. ocf1b is cleared by the hardware when exe- cuting the corresponding interrupt handling vector. alternatively, ocf1b is cleared by writing a logic one to the flag. when the i-bit in sr eg, and ocie1b (timer/counter1 compare match interruptb enable), and the ocf1b are set (one), the timer/counter1 compare b match inter- rupt is executed. bit 4 ? res: reserved bit this bit is a reserved bit in the at43usb351m and always reads zero. bit 3 ? icf1: - input capture flag 1 the icf1 bit is set (one) to flag an input capture event, indicating that the timer/counter1 value has been transferred to the input capture register - icr1. icf1 is cleared by the hard- ware when executing the corresponding interrupt handling vector. alternatively, icf1 is cleared by writing a logic one to the flag. when the sreg i-bit, and ticie1 (timer/counter1 input capture interrupt enable), and icf1 are set (one), the timer/counter1 capture interrupt is executed. bit 2 ? res: reserved bit this bit is a reserved bit in the at43usb351m and always reads zero. bit 1 ? tov: timer/counter0 overflow flag the bit tov0 is set (one) when an overflow occu rs in timer/counter0. tov0 is cleared by the hardware when executing the corresponding interr upt handling vector. alternatively, tov0 is cleared by writing a logic one to the flag. when the sreg i- bit, and toie0 (timer/counter0 overflow interrupt enable), and tov0 are set (one), the timer/counter0 overflow interrupt is executed. bit 0 ? res: reserved bit this bit is a reserved bit in the at43usb351m and always reads zero. bit 7 6 5 4 3 210 $38 ($58) tov1 ocf1a ocifb ? icf1 ? tov0 ? tifr read/write r/w r/w r/w r r/w r r/w r initial value 0 0 0 0 0 0 0 0
28 at43usb351m 3302e?usb?7/04 external interrupts the external interrupts are triggered by the int0/int1 pins. observe that, if enabled, the int0/int1 interrupts will trigger even if the int0/int1 pins are co nfigured as out puts. this fea- ture provides a way of generating a software interrupt. the external interrupts can be triggered by a falling or rising edge or a low level. this is set up as indicated in the specification for the mcu control register (mcucr) and the inte rrupt sense control register (iscr). when int0/int1 is enabled and is configured as level tr iggered, the interrupt will trigger as long as the pin is held low. int0/int1 is set up as des cribed in the specification for the mcu control register (mcucr). interrupt response time the interrupt execution response for all the enabled avr interrupts is 4 clock cycles minimum. 4 clock cycles after the interrupt flag has been set, the program vector address for the actual interrupt handling routine is executed. during this 4 clock cycle period, the program counter (2 bytes) is pushed onto the stack, and the stack pointer is decremented by 2. the vector is nor- mally a jump to the interrupt routine, and this jump takes 3 clock cycles. if an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. a return from an interrupt handling routine (same as for a subroutine call routine) takes 4 clock cycles. during these 4 clock cycles, the progra m counter (2 bytes) is popped back from the stack, the stack pointer is incremented by 2, and the i flag in sreg is set. when the avr exits from an interrupt, it will always return to the main prog ram and execute one more instruc- tion before any pending interrupt is served.
29 at43usb351m 3302e?usb?7/04 mcu control re gister ? mcucr bit 7, 6 ? res: reserved bits bit 5 ? se: sleep enable the se bit must be set (1) to make the mcu enter the sleep mode when the sleep instruc- tion is executed. to avoid the mcu entering th e sleep mode, unless it is the programmer's purpose, it is recommended to set the sleep enable se bit just before the execution of the sleep instruction. bit 4 ? sm: sleep mode this bit selects between the two available sleep modes. when sm is cleared (zero), idle mode is selected as sleep mode. when sm is set (1), power down mode is selected as sleep mode. the at43usb351m does not support the idle mode and sm should always be set to one when entering the sleep mode. bit 3, 2 ? isc11, isc10: interrupt sense control 1 bit 1 and bit 0 the external interrupt 1 is activated by the external pin int1 if the sreg i-flag and the corre- sponding interrupt mask in the gimsk is set. the level and edges on the external int1 pin that activate the interrupt are defined in the following table: bit 1, 0 ? isc01, isc00: interrupt sense control 0 bit 1 and bit 0 the external interrupt 0 is activated by the external pin int0 if the sreg i-flag and the corre- sponding interrupt mask in the gimsk is set. the level and edges on the external int0 pin that activate the interrupt are defined in table 9. bit 7 6 5 4 3 2 1 0 $35 ($55) ? ? se sm isc11 isc10 isc01 isc00 mcucr read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 8. int1 sense control isc11 isc10 description 0 0 the low level of int1 generates an interrupt request. 01reserved. 1 0 the falling edge of int1 generates an interrupt request. 1 1 the rising edge of int1 generates an interrupt request. table 9. int0 sense control isc01 isc00 description 0 0 the low level of int0 generates an interrupt request. 01reserved. 1 0 the falling edge of int0 generates an interrupt request. 1 1 the rising edge of int0 generates an interrupt request.
30 at43usb351m 3302e?usb?7/04 usb interrupt sources the usb interrupts are described below. all interrupts have individual enable, status, and mask bits through the interrupt enable regis- ter and interrupt mask register. the suspend and resume interrupts are cleared by writing a 0 to the particular interrupt bit. all other interrupts are cleared when the microcontroller sets a bit in an interrupt acknowledge register. table 10. usb interrupt sources interrupt description sof received whenever usb hardware decodes a valid start of frame. the frame number is stored in th e two frame number registers. function ep0 interrupt see ?control transfers at control endpoint ep0? on page 72 for details. function ep1 interrupt for an out endpoint it indicates that function endpoint 1 has received a valid out packet and that the data is in the fifo. for an in endpoint it means that the endpoint has received an in token, sent out the data in the fifo and received an ack from the host. the fifo is now ready to be written by new data from the microcontroller. function ep2 interrupt for an out endpoint it indicates that function endpoint 2 has received a valid out packet and that the data is in the fifo. for an in endpoint it means that the endpoint has received an in token, sent out the data in the fifo and received an ack from the host. the fifo is now ready to be written by new data from the microcontroller. function ep3 interrupt for an out endpoint it indicates that function endpoint 3 has received a valid out packet and that the data is in the fifo. for an in endpoint it means that the endpoint has received an in token, sent out the data in the fifo and received an ack from the host. the fifo is now ready to be written by new data from the microcontroller. function ep4 interrupt for an out endpoint it indicates that function endpoint 4 has received a valid out packet and that the data is in the fifo. for an in endpoint it means that the endpoint has received an in token, sent out the data in the fifo and received an ack from the host. the fifo is now ready to be written by new data from the microcontroller. frwup usb hardware has received a embedded function remote wakeup request. glb susp usb hardware has received global suspend signaling and is preparing to put the hub in the suspend mode. the microcontroller's firmware should place the embedded function in the suspend state. rsm usb hardware received resume signaling and is propagating the resume signaling. the microcontroller's firmware should take the embedded function out of the suspended state. bus reset usb hardware received a u sb bus reset. this applies only in cases where a separation between usb bus reset and microcontroller reset is required. be very careful when using this feature.
31 at43usb351m 3302e?usb?7/04 usb endpoint interrupt sources an assertion or activation of one or more bits in the endpoint's control and status register triggers the endpoint interrupts. these triggers are different for control and non-control end- points as described in the table below. please refer to the control and status register for more information. usb interrupt status register ? uisr bit 7 ? sof int: start of frame interrupt this bit is asserted after the usb hardware receives a valid sof packet. bit 6, 5 ? res: reserved bit these bits are reserved and always read as zero. bit 4 ? fep4 int: function endpoint 4 interrupt bit 3 ? fep3 int: function endpoint 3 interrupt bit 2 ? fep2 int: function endpoint 2 interrupt bit 1 ? fep1 int: function endpoint 1 interrupt bit 0 ? fep0 int: function endpoint 0 interrupt the hub and function interrupt bits will be set by the hardware whenever the following bits in the corresponding endpoint's control and status register are modified by the usb hardware: 1. rx out packet is set (control and out endpoints) 2. tx packet ready is cleared and tx comp lete is set (control and in endpoints) 3. rx setup is set (control endpoints only) 4. tx complete is set table 11. usb endpoint interrupt sources bit endpoint type rx_out_packet control, out tx_complete control, in stall_sent control, in rx_setup control bit 7 6 5 4 3 2 1 0 $1ff7 sof int ? ? fe4 int fe3 int fe2 int fe1 int fe0 int uisr read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0
32 at43usb351m 3302e?usb?7/04 usb interrupt mask register ? uimskr bit 7 ? sof imsk: enable start of frame interrupt mask when the sof imsk bit is set (1), the start of frame interrupt is masked. bit 6, 5 ? res: reserved bit these bits are reserved and always read as zero. bit 4 ? fep4 imsk: enable function endpoint 4 interrupt when the fe4 imsk bit is set (1), the function endpoint 4 interrupt is masked. bit 3 ? fep3 imsk: function endpoint 3 interrupt when the fep3 imsk bit is set (1), the function endpoint 3 interrupt is masked. bit 2 ? fep2 imsk: enable endpoint 2 interrupt when the fe2 imsk bit is set (1), the function endpoint 2 interrupt is masked. bit 1 ? fep1 imsk: enable endpoint 1 interrupt when the fe1 imsk bit is set (1), the function endpoint 1 interrupt is masked. bit 0 ? fep0 imsk: enable endpoint 0 interrupt when the fe0 imsk bit is set (1), the function endpoint 0 interrupt is masked. bit 7 6 5 4 3 2 1 0 $1ff6 sof imsk ? ? fep4 imsk fep3 imsk fep2 imsk fep1 imsk fep0 imsk uimskr read/write r/w r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
33 at43usb351m 3302e?usb?7/04 usb interrupt acknowledge register ? uiar bit 7 ? sof intack: start of frame interrupt acknowledge the microcontroller firmware writes a 1 to this bit to clear the sof int bit. bit 6, 5 ? res: reserved bit these bits are reserved and are always read as zero. bit 4 ? fep4 intack: function endpoint 4 interrupt acknowledge the microcontroller firmware writes a 1 to this bit to clear the fep4 int bit. bit 3 ? fep3 intack: function endpoint 3 interrupt acknowledge the microcontroller firmware writes a 1 to this bit to clear the fep3 int bit. bit 2 ? fep2 intack: function endpoint 2 interrupt acknowledge the microcontroller firmware writes a 1 to this bit to clear the fep2 bit. bit 1 ? fep1 intack: function endpoint 1 interrupt acknowledge the microcontroller firmware writes a 1 to this bit to clear the fep1 bit. bit 0 ? fep0 intack: function endpoint 0 interrupt acknowledge the microcontroller firmware writes a 1 to this bit to clear the fep0 int bit. bit 7 6 5 4 3 2 1 0 $1ff5 sof intack ? ? fep4 intack fep3 intack fep2 imsk fep1 intack fep0 intack uiar read/write w r r w w w w w initial value 0 0 0 0 0 0 0 0
34 at43usb351m 3302e?usb?7/04 usb interrupt enable register ? uier bit 7 ? sof ie: enable start of frame interrupt when the sof ie bit is set (1), the start of frame interrupt is enabled. bit 6, 5 ? res: reserved bits these bits are reserved and always read as zero. bit 4 ? fep4 ie: enable function endpoint 4 interrupt when the fe4 ie bit is set (1), the function endpoint 4 interrupt is enabled. bit 3 ? fep3 ie: function endpoint 3 interrupt when the fep3 ie bit is set (1), the function endpoint 3 interrupt is enabled. bit 2 ? fep2 ie: enable endpoint 2 interrupt when the fe2 ie bit is set (1), the function endpoint 2 interrupt is enabled. bit 1 ? fep1 ie: enable endpoint 1 interrupt when the fe1 ie bit is set (1), the function endpoint 1 interrupt is enabled. bit 0 ? fep0 ie: enable endpoint 0 interrupt when the fe0 ie bit is set (1), the function endpoint 0 interrupt is enabled. suspend/resume register ? sprsr bit 7..4 ? res: reserved bits these bits are reserved and are always read as zeros. bit 3 ? bus int: usb bus interrupt when the usb reset separation feature is enabled (sprsie and sprsmsk bits 3 are set to 1) the bus int bit is set when usb bus reset is detected by the usb hardware. bit 2 ? frwup: function remote wakeup the usb hardware sets this bit to signal that external interrupt 1 is detected indicating remote wakeup. an interrupt is generated if the frwup ie bit of the sprsie register is set. bit 1 ? rsm: resume the usb hardware sets this bit when a usb resume signaling is detected at any of its port except port 1. an interrupt is generated if the rsm ie bit of the sprsie register is set. bit 0 ? glb susp: global suspend the usb hardware sets this bit when a usb global suspend signaling is detected. an interrupt is generated if the glbsusp ie bi t of the sprsie register is set. bit 7 6 5 4 3 2 1 0 $1ff3 sof ie ? ? fep4 ie fep3 ie fep2 ie fep1 ie fep0 ie uier read/write r/w r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit76543 2 1 0 $1ffa ? ? ? ? bus int frwup rsm glb susp sprsr read/write r r r r r/w r r r initial value 0 0 0 0 0 0 0 0
35 at43usb351m 3302e?usb?7/04 suspend/resume interrupt enable register ? sprsie bit 7..4 ? res: reserved bits these bits are reserved and are always read as zeros. bit 3 ? bus int en: usb reset interrupt enable when the bus int en bit is set, the usb and mi crocontroller resets are separated. a usb bus reset will reset the usb hardwar e only and not the microcontro ller. however, an interrupt to the microcontroller will be gene rated and bit 3 of sprsr is set. bit 2 ? frwup ie: function remote wakeup interrupt enable setting the frwup ie bit will initia te an interrupt whenever th e frwup bit of sprsr is set. bit 1 ? rsm ie: resume interrupt enable setting the rsm ie bit will initiate an interrupt whenever the rsm bit of sprsr is set. bit 0 ? glb susp ie: globa l suspend interrupt enable setting the glb susp ie bit will initiate an inte rrupt whenever the glb susp bit of sprsr is set. suspend/resume interrupt mask register ? sprsmsk the bits of the suspend/resume mask register are used to make an interrupt caused by an event in the suspend/resume register visibl e to the microcontroller. the suspend/resume interrupt enable register bits enable the interrupt while the suspend/resume interrupt mask register allows the microcontrolle r to control when it wants visi bility to an interr upt. 1 = enable mask, 0 = disable mask. bit 7..4 ? res: reserved bits these bits are reserved and are always read as zeros. bit 3 ? bus int msk: usb reset interrupt mask bit 2 ? frwup msk: function remote wakeup interrupt mask bit 1 ? rsm msk: resume interrupt mask bit 0 ? glb susp msk: global suspend interrupt enable bit 7 6 5 4 3 2 1 0 $1ff9 ? ? ? ? bus int frwup rsm glb susp sprsie read/write r r r r r/w r r r initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 $1ff8 ? ? ? ? bus int msk frwup msk rsm glb susp sprsmsk read/write r r r r w w w w initial value 0 0 0 0 0 0 0 0
36 at43usb351m 3302e?usb?7/04 avr register set status register and stack pointer status register ? sreg bit 7 ? i: global interrupt enable the global interrupt enable bit must be set (one) for the interrupts to be enabled. the individ- ual interrupt enable control is then performed in separate control registers. if the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings . the i-bit is cleared by the hardware after an interrupt has occurred, and is set by the reti instruction to enable subsequent interrupts. bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (bit store) use the t bit as source and des- tination for the operated bit. a bit from a register in the register file can be copied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. bit 5 ? h: half carry flag the half carry flag h indicates a half carry in some arithmetic operations. see the instruction set description for detailed information. bit 4 ? s: sign bit, s = n v the s-bit is always an exclusive or between the negative flag n and the two's complement overflow flag v. see the instruction set description for detailed information. bit 3 ? v: two's complement overflow flag the two's complement overflow flag v supports two's complement arithmetics. see the instruction set descriptio n for detailed information. bit 2 ? n: negative flag the negative flag n indicates a negative result after the different arithmetic and logic opera- tions. see the instruction set description for detailed information. bit 1 ? z: zero flag the zero flag z indicates a zero result after the different arithmetic and logic operations. see the instruction set descripti on for detailed information. bit 0 ? c: carry flag the carry flag c indicates a carry in an arithmetic or logic operation. see the instruction set description for de tailed information. note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. this must be handled by software. bit 7 6 5 4 3 2 1 0 $3f ($5f) ithsvnzcsreg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
37 at43usb351m 3302e?usb?7/04 stack pointer register ? sp the stack pointer points to the data sram stack area where the subroutine and interrupt stacks are located. this stack space in the data sram must be defined by the program before any subroutine calls are executed or interrupts are enabled. the stack pointer must be set to point above $60. the stack pointer is decremented by one when data is pushed onto the stack with the push instruction, and it is decremented by two when an address is pushed onto the stack with subroutine calls and interrupts. the stack pointer is incremented by one when data is popped from the stack with the pop instruction and it is incremented by two when an address is popped from the stack with return from subroutine ret or return from interrupt reti. sleep modes to enter the sl eep modes, the se bit in mcucr must be set (one) and a sleep instruction must be executed. if an enabled interrupt occurs while the mcu is in a sleep mode, the mcu awakes, executes the interrupt routine, and resumes execution from the instruction following sleep. the contents of the register file, sr am and i/o memory are unaltered. if a reset occurs during sleep mode, the mcu wakes up and executes from the reset vector. power down mode when the sm bit is set (one), the sleep instruction forces the mcu into the power down mode. in this mode, the external oscillator is stopped, while the external interrupts continue operating. only an external reset, an external level interrupt on int0 or int1, can wake up the mcu. note that when a level triggered interrupt is used for wake-up from power down, the low level must be held for a time longer than the reset delay time-out period t tout . otherwise, the mcu will fail to wake up. bit 1514131211109 8 $3e ($5e) ithsvnzcsph $3d ($5d) sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl 76 5 4 3210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 00 0 0 0000
38 at43usb351m 3302e?usb?7/04 timer/counters the at43usb351m provides two general-purpo se timer/counters - one 8-bit t/c and one 16-bit t/c. the timer/counters have individual prescaling selection from the same 10-bit prescaling timer. both timer/counters can either be used as a timer with an internal clock timebase or as a counter with an external pin connection which triggers the counting. timer/counter prescaler the four different prescaled selections are: ck/8, ck/64, ck/256 and ck/1024 where ck is the oscillator clock. for the two timer/counters , added selections as ck, external source and stop, can be selected as clock sources. note: when the at43usb351m mcu is operating at 24 mhz, the mcu clock frequency is halved before it is used in the timer/counter prescale r circuit. the source clock for the timer/counter is always 12 mhz. figure 10. timer/counter prescaler 10-bit t/c prescaler cs00 cs01 cs02 cs10 cs11 cs12 0 0 ck t0 t1 ck/8 ck/64 ck/256 ck/1024 timer/counter1 clock source tck1 timer/counter0 clock source tck0
39 at43usb351m 3302e?usb?7/04 8-bit timer/counter0 the 8-bit timer/counter0 can select clock source from ck, prescaled ck or an external pin. in addition it can be stopped as described in the specification for the timer/counter0 control register (tccr0). the overflow status flag is found in the timer/counter interrupt flag regis- ter (tifr). control signals are found in the timer/counter0 control register (tccr0). the interrupt enable/disable settings for timer/counter0 are found in the timer/counter interrupt mask register - timsk. when timer/counter0 is externally clocked, th e external signal is synchronized with the oscil- lator frequency of the cpu. to assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal cpu clock period. the external clock signal is sampled on the rising edge of the internal cpu clock. the 8-bit timer/counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportunities. similarly, the high prescaling opportunities make the timer/counter0 useful for lower speed functions or exact timing functions with infrequent actions. figure 11. timer/counter0 block diagram control logic timer/counter0 (tcnt0) timer int. mask register (timsk) timer int. flag register (tifr) t/c0 control register (tccr0) toie1 oicie1a oicie1b ticie1 toie0 tov1 ocf1a ocf1b icf1 tov0 cs02 cs01 cs00 t/c clock source tov0 70 ck t0 t/c0 overflow irq 8-bit data bus
40 at43usb351m 3302e?usb?7/04 timer/counter0 control register ? tccr0 bits 7..3 ? res: reserved bits these bits are reserved bits in the at43usb351m and always read as zero. bits 2, 1, 0 ? cs02, cs01, cs00: clock select0, bit 2, 1 and 0 the clock select0 bits 2, 1 and 0 define the prescaling source of timer/counter0. the stop condition provides a timer enable/disable function. the ck down divided modes are scaled directly from the ck oscillator clock. if the external pin modes are used for timer/counter0, transitions on pb0 /(t0) will clock the counter even if the pin is configured as an output. this feature can give the user sw control of the counting. timer/counter0 ? tcnt0 the timer/counter0 is realized as an up-counter with read and write access. if the timer/counter0 is written and a clock source is present, the timer/counter0 continues count- ing in the clock cycle following the write operation. bit7654321 0 $33 ($53) ? ? ? ? ? cs02 cs01 cs00 tccr0 read/write r r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 12. clock 0 prescale select cs02 cs01 cs00 description 0 0 0 stop, the timer/counter0 is stopped 001ck 010ck/8 011ck/64 100ck/256 101ck/1024 1 1 0 external pin t0, falling edge 1 1 1 external pin t0, rising edge bit 7 6 5 4 3 2 1 0 $32 ($52) msb ? ? ? ? ? ? lsb tcnt0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
41 at43usb351m 3302e?usb?7/04 16-bit timer/counter1 figure 12. timer/counter1 block diagram control logic timer int. mask register (timsk) t/c1 control register a (tccr1a) t/c1 control register b (tccr1b) toie1 ocie1a ocie1b ticie1 toie0 com1a1 com1a0 com1b1 icf1 pwm11 cs12 cs11 cs10 ck t1 t/c1 overflow irq 8-bit data bus 7 0 t/c1 input capture register (icr1) 8 15 timer/counter1 (tcnt1) 16-bit comparator timer/counter1 output compare register a 16-bit comparator timer/counter1 output compare register b 7 0 8 15 7 0 8 15 7 0 8 15 0 15 7 0 8 15 7 8 t/c1 compare matcha irq t/c1 compare matchb irq t/c1input capture irq tov1 ocf1a ocf1b icf1 tov0 tov1 timer int. flag register (tifr) ctc1 icnc1 ices1 com1b0 ocf1a ocf1b pwm10 capture trigger
42 at43usb351m 3302e?usb?7/04 16-bit timer/counter1 operation the 16-bit timer/counter1 can select clock source from ck, prescaled ck or an external pin. in addition, it can be stopped as described in the specification for the timer/counter1 control registers (tccr1a and tccr1b). the different status flags (overflow, compare match and capture event) are found in the timer/counter interrupt flag register (tifr). control signals are found in the timer/counter1 control registers (tccr1a and tccr1b). the interrupt enable/disable settings for timer/counter1 ar e found in the timer/counter interrupt mask register (timsk). when timer/counter1 is externally clocked, th e external signal is synchronized with the oscil- lator frequency of the cpu. to assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal cpu clock period. the external clock signal is sampled on the rising edge of the internal cpu clock. the 16-bit timer/counter1 features both a high resolution and a high accuracy usage with the lower prescaling opportunities. similarly, the high prescaling opportunities makes the timer/counter1 useful for lower speed functions or exact timing functions with infrequent actions. the timer/counter1 supports two output compare functions using the output compare reg- ister 1 a and b (ocr1a and ocr1b) as the data sources to be compared to the timer/counter1 contents. the output compare functions include optional clearing of the counter on comparea match, and actions on the output compare pins on both compare matches. timer/counter1 can also be used as a 8-, 9- or 10-bit pulse with modulator. in this mode the counter and the ocr1a/ocr1b registers serve as a dual glitch-free stand-alone pwm with centered pulses. the input capture function of timer/counter1 pr ovides a capture of the timer/counter1 con- tents to the input capture register - icr1, triggered by an external event on the input capture pin (icp/port pd4). the actual capture event se ttings are defined by the timer/counter1 con- trol register (tccr1b). in addition, the analog comparator can be set to trigger the input capture. if the noise canceler function is enabled, the ac tual trigger condition for the capture event is monitored over 4 samples, and all 4 must be equal to activate the capture flag. figure 13. icp pin schematic diagram icp 0 1 noise canceler edge select icnc1 ices1 icf1 acic aco acic: comparator ic enable acc0: comparator output
43 at43usb351m 3302e?usb?7/04 timer/counter1 control register a ? tccr1a bits 7, 6 ? com1a1, com1a0: compare outp ut mode1a, bits 1 and 0 the com1a1 and com1a0 control bits determine any output pin action following a compare match in timer/counter1. any output pin actions affect pin oc1a (output comparea) pin 1. this is an alternative function to an i/o port an d the corresponding direction control bit must be set (one) to control the output pin. the control configuration is shown in table 13. bits 5, 4 ? com1b1, com1b0: compare ou tput mode1b, bits 1 and 0 the com1b1 and com1b0 control bits determine any output pin action following a compare match in timer/counter1. any output pin actions affect pin oc1b (output compareb). the fol- lowing control configuration is given: note: 1. x = a or b 2. in pwm mode, these bits have a different function. refer to table 17 for a detailed description. bits 3..2 ? res: reserved bits these bits are reserved bits in the at43usb351m and always read zero. bits 1..0 ? pwm11, pwm10: pulse width modulator select bits 1 and 0 these bits select pwm operation of timer/counter1 as specified in table 14. bit 7 6543210 $2f ($4f) com1a1 com1a0 com1b1 com1b0 ? ? pwm11 pwm10 tccr1a read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 13. compare 1 mode select (2) com1x1 com1x0 description 0 0 timer/counter1 disconnected from output pin oc1x. (1) 0 1 toggle the oc1x output line. (1) 1 0 clear the oc1x output line (to zero). (1) 1 1 set the oc1x output line (to one). (1) table 14. pwm mode select pwm11 pwm10 description 0 0 pwm operation of timer/counter1 is disabled. 0 1 timer/counter1 is an 8-bit pwm. 1 0 timer/counter1 is a 9-bit pwm. 1 1 timer/counter1 is a 10-bit pwm.
44 at43usb351m 3302e?usb?7/04 timer/counter1 control register b ? tccr1b bit 7 ? icnc1: input capture1 no ise canceler (4 cks) when the icnc1 bit is cleared (zer o), the input capture trigger noi se canceler function is dis- abled. the input capture is triggered at the first rising/falling edge sampled on the icp (input capture pin) as specified. when the icnc1 bit is set (one), four succ essive samples are mea- sured on the icp and all samples must be high/low according to the input capture trigger specification in the ices1 bit. the actual sampling frequency is the 12 mhz system clock frequency. bit 6 ? ices1: input capture1 edge select while the ices1 bit is cleared (zero), the timer/counter1 contents are transferred to the input capture register (icr1) on the falling edge of the icp. while the ices1 bit is set (one), the timer/counter1 contents are transferred to the icr1 on the rising edge of the icp. bits 5, 4 ? res: reserved bits these bits are reserved bits in the at43usb351m and always read zero. bit 3 ? ctc1: clear timer/counter1 on compare match when the ctc1 control bit is set (one), the timer/counter1 is reset to $0000 in the clock cycle after a comparea match. if the ctc1 control bit is cleared, timer/counter1 continues counting and is unaffected by a compare match. since th e compare match is detected in the cpu clock cycle following the match, this function will behave diff erently when a prescaling higher than 1 is used for the timer. when a prescaling of 1 is used, and the comparea register is set to c, the timer will count as fo llows if ctc1 is set: ... | c-2 | c-1 | c | 0 | 1 | ... when the prescaler is set to divide by 8, the timer will count like this: ... | c-2, c-2, c-2, c-2, c-2, c-2, c-2, c-2 | c-1, c-1, c-1, c-1, c-1, c-1, c-1, c-1 | c, 0, 0, 0, 0, 0, 0, 0 | ... in pwm mode, this bit has no effect. bits 2, 1, 0 ? cs12, cs11, cs10: clock select1, bit 2, 1 and 0 the clock select1 bits 2, 1 and 0 define the prescaling source of timer/counter1. bit 7 6543210 $2e ($4e) icnc1 ices1 ? ? ctc1 cs12 cs11 cs10 tccr1b read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 15. clock 1 prescale select cs12 cs11 cs10 description 0 0 0 stop, the timer/counter1 is stopped. 001ck 010ck/8 011ck/64 100ck/256
45 at43usb351m 3302e?usb?7/04 the stop condition provides a timer enable/disable function. the ck down divided modes are scaled directly from the 12 mhz system cl ock. if the external pin modes are used for timer/counter1, transitions on pb1 /(t1) will clock the counter even if the pin is configured as an output. this feature can give the user sw control of the counting. 101ck/1024 1 1 0 external pin t1, falling edge 1 1 1 external pin t1, rising edge table 15. clock 1 prescale select (continued) cs12 cs11 cs10 description
46 at43usb351m 3302e?usb?7/04 timer/counter1 ? tcnt1h and tcnt1l this 16-bit register contains the prescaled va lue of the 16-bit timer/counter1. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access is performed using an 8-bit temporary register (temp). this tem- porary register is also used when accessing ocr1a, ocr1b and icr1. if the main program and also interrupt routines perform access to registers using temp, interrupts must be dis- abled during access from the main program and from interrupt routines if interrupts are allowed from within interrupt routines. tcnt1 timer/counter1 write: when the cpu writes to the high byte tcnt1h, the written data is placed in the temp regis- ter. next, when the cpu writes the low byte tcnt 1l, this byte of data is combined with the byte data in the temp register, and all 16 bits are written to the tcnt1 timer/counter1 regis- ter simultaneously. consequently, the high byte tcnt1h must be accessed first for a full 16- bit register write operation. tcnt1 timer/counter1 read: when the cpu reads the low byte tcnt1l, the data of the low byte tcnt1l is sent to the cpu and the data of the high byte tcnt1h is placed in the temp register. when the cpu reads the data in the high byte tcnt1h, the cpu receives the data in the temp register. consequently, the low byte tcnt1l must be accessed first for a full 16-bit register read operation. the timer/counter1 is realized as an up or up/down (in pwm mode) counter with read and write access. if timer/counter1 is written to and a clock source is selected, the timer/counter1 continues counting in the timer clock cycle after it is preset with the written value. bit 1514131211109 8 $2d ($4d) msb ? ? ? ? ? ? ? tcnt1h $2c ($4c) ? ? ? ? ? ? ? lsb tcnt1l 76 5 4 3210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 00 0 0 0000
47 at43usb351m 3302e?usb?7/04 timer/counter1 output compare register ? ocr1ah and ocr1al timer/counter1 output compare register ? ocr1bh and ocr1bl the output compare registers are 16-bit read/write registers. the timer/counter1 output compare registers contain the data to be continuously compared with timer/counter1. actions on compare matches are specified in the timer/counter1 con- trol and status register.a compare match does only occur if timer/counter1 counts to the ocr value. a software write that sets tcnt1 and ocr1a or ocr1b to the same value does not generate a compare match. a compare match will set the comp are interrupt flag in the cpu clock cycle following the com- pare event. since the output compare registers ocr1a and ocr1b are 16-bit registers, a temporary register temp is used when ocr1a/b are written to ensure that both bytes are updated simultaneously. when the cpu writes the high byte, ocr1ah or ocr1bh, the data is tempo- rarily stored in the temp register. when the cpu writes the low byte, ocr1al or ocr1bl, the temp register is simultaneously written to ocr1ah or ocr1bh. consequently, the high byte ocr1ah or ocr1bh must be written firs t for a full 16-bit register write operation. the temp register is also used when accessi ng tcnt1, and icr1. if the main program and also interrupt routines perform access to registers using temp, interrupts must be disabled during access from the main program and from interrupt routines if interrupts are allowed from within interrupt routines. bit 15 14 13 12 11 10 9 8 $2b ($4b) msb???????ocr1ah $2a ($4a) ???????lsbocr1al 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 00000000 bit 1514131211109 8 $29 ($49) msb???????ocr1bh $28 ($48) ???????lsbocr1bl 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 00000000
48 at43usb351m 3302e?usb?7/04 timer/counter1 input capture register ? icr1h and icr1l the input capture register is a 16-bit read-only register. when the rising or falling edge (according to the inpu t capture edge setting - ices1) of the sig- nal at the input capture pin (icp) is detected, the current value of the timer/counter1 is transferred to the input capture register (icr1). at the same time, the input capture flag (icf1) is set (one). since the icr1 is a 16-bit register, a temporary register temp is used when icr1 is read to ensure that both bytes are read simultaneously. when the cpu reads the low byte icr1l, the data is sent to the cpu and the data of the high byte icr1h is placed in the temp register. when the cpu reads the data in the high byte icr1h, the cpu receives the data in the temp register. consequently, the low byte icr1l must be accessed first for a full 16-bit register read operation. the temp register is also used when accessing tcnt1, ocr1a and ocr1b. if the main pro- gram and also interrupt routines perform access to registers using temp, interrupts must be disabled during access from the main program and from interrupt routines, if interrupts are allowed from within interrupt routines. timer/counter1 in pwm mode when the pwm mode is selected, timer/counter1, the output compare register1a (ocr1a) and the output compare register1b (ocr1b) form a dual 8-, 9- or 10-bit, free-running, glitch- free and phase correct pwm with output s on the pd5 (oc1a) and oc1b pins. timer/counter1 acts as an up/down counter, co unting up from $0000 to top (see table 16), where it turns and counts down again to zero before the cycle is repeated. when the counter value matches the contents of the 10 least si gnificant bits of ocr1a or ocr1b, the pd5(oc1a)/oc1b pins are set or cleared according to the settings of the com1a1/com1a0 or com1b1/com1b0 bits in the timer/counter1 control register tccr1a. refer to table 17 for details. bit 1514131211109 8 $25 ($45) msb ? ? ? ? ? ? ? icr1h $24 ($44) ?? ? ? ???lsbicr1l 76 5 4 3210 read/write r r r r r r r r rr r r rrrr initial value 0 0 0 0 0 0 0 0 00 0 0 0000 table 16. timer top values and pwm frequency pwm resolution timer top value frequency 8-bit $00ff (255) f tck1 /510 9-bit $01ff (511) f tck1 /1022 10-bit $03ff(1023) f tck1 /2046
49 at43usb351m 3302e?usb?7/04 note: x = a or b note that in the pwm mode, the 10 least significant ocr1a/ocr1b bits, when written, are transferred to a temporary location. they are latched when timer/counter1 reaches the value top. this prevents the occurrence of odd-length pwm pulses (glitches) in the event of an unsynchronized ocr1a/ocr1b write. see figure 14 for an example. figure 14. effects on unsynchronized ocr1 latching note: x = a or b during the time between the write and the latc h operation, a read from ocr1a or ocr1b will read the contents of the temporary location. this means that the most recently written value always will read out of ocr1a/b when the ocr1 contains $0000 or top, the output oc1a/oc1b is updated to low or high on the next compare match, according to the settings of com1a1/com1a0 or com1b1/com1b0. this is shown in table 18. note: if the compare register contains the top value and the prescaler is not in use (cs12..cs10 = 001), the pwm output will not pr oduce any pulse at all, because up-counting and down-counting values are reached simultaneously. when the prescaler is in use table 17. compare1 mode select in pwm mode com1x1 com1x0 effect on ocx1 0 0 not connected 0 1 not connected 10 cleared on compare match, up-counting. set on compare match, down-counting (non-inverted pwm). 11 cleared on compare match, down-cou nting. set on compare match, up-counting (inverted pwm). synchronized ocr1x latch pwm output oc1x counter value compare value pwm output oc1x counter value compare value unsynchronized ocr1x latch glitch compare value changes compare value changes
50 at43usb351m 3302e?usb?7/04 (cs12..cs10 = 001 or 000), the pwm output goes active when the counter reaches the top value, but the down-counting compare match is not interpreted to be reached before the next time the counter reaches the top value, making a one-period pwm pulse. note: x = a or b in pwm mode, the timer overflow flag1, to v1, is set when the counter advances from $0000. timer overflow interrupt1 operates exactly as in normal timer/counter mode, i.e. it is executed when tov1 is set provided that time r overflow interrupt1 and global interrupts are enabled. this also applies to the timer output compare1 flags and interrupts. watchdog timer the watchdog timer is clocked from a 1 mhz cl ock derived from the 6 mhz on chip oscillator. by controlling the watchdog time r prescaler, the watchdog rese t interval can be adjusted, see table 19 for a detailed description. the wdr (watchdog reset) instruction resets the watchdog timer. eight different clock cycle periods can be selected to determine the reset period. if the reset period expires without another watchdog reset, the at43usb351m resets and executes from the reset vector. to prevent unintentional disabling of the watc hdog, a special turn-off sequence must be fol- lowed when the watchdog is disabled. refer to the description of the watchdog timer control register for details. figure 15. watchdog timer table 18. pwm outputs ocr1x = $0000 or top com1x1 com1x0 ocr1x output oc1x 1 0 $0000 l 10top h 1 1 $0000 h 11top l osc/16k osc/32k osc/64k osc/128k osc/256k osc/512k osc/1024k osc/2048k 1 mhz clock mcu reset wde wdp2 wdp1 wdp0 watchdog reset watchdog prescaler
51 at43usb351m 3302e?usb?7/04 watch dog timer control register ? wdtcr bits 7..5 ? res: reserved bits these bits are reserved bits in the at 43usb351m and will always read as zero. bit 4 ? wdtoe: watch dog turn-off enable this bit must be set (one) wh en the wde bit is cleared. othe rwise, the watchdog will not be disabled. once set, the hardware will clear this bi t to zero after four cl ock cycles. refer to the description of the wde bit for a watchdog disable procedure. bit 3 ? wde: watch dog enable when the wde is set (one) the watchdog timer is enabled, and if the wde is cleared (zero) the watchdog timer function is disabled. wde can only be cleared if the wdtoe bit is set (one). to disable an enabled watchdog timer, the following procedure must be followed: 1. in the same operation, write a logical one to wdtoe and wde. a logical one must be written to wde even though it is set to one before the disable operation starts. 2. within the next four clock cycles, write a logical 0 to wde. this disables the watchdog. bits 2..0 ? wdp2, wdp1, wdp0: watch dog timer prescaler 2, 1 and 0 the wdp2, wdp1 and wdp0 bits determine the watchdog timer prescaling when the watchdog timer is enabled. the different prescaling values and their corresponding time-out periods are shown in table 19. note: the wdr (watchdog reset) instruction shoul d always be executed before the watchdog timer is enabled. this ensures that the reset peri od will be in accordance with the watchdog timer prescale settings. if the watchdog timer is enabled without reset, the watchdog timer may not start to count from zero. to avoid unintentional mcu reset, the watchdog timer should be dis- abled or reset before changing the watchdog timer prescale select. bit 7 6 5 4 3 2 1 0 $21 ($41) ? ? ? wdtoe wde wdp2 wdp1 wdp0 wdtcr read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 19. watchdog timer prescale select wdp2 wdp1 wdp0 number of wdt oscillator cycles time-out 0 0 0 8k cycles 8.2 ms 0 0 1 16k cycles 16.4 ms 0 1 0 32k cycles 33.8 ms 0 1 1 64k cycles 65.6 ms 1 0 0 128k cycles 0.131 s 1 0 1 256k cycles 0.262 s 1 1 0 512k cycles 0.524 s 1 1 1 1,024k cycles 1.048 s
52 at43usb351m 3302e?usb?7/04 serial peripheral interface (spi) the serial peripheral interface (spi) allows high-speed synchronous data transfer between the at43usb351m and peripheral devices or between several avr devices. the at43usb351m spi features include the following: full-duplex, 3-wire synchronous data transfer master or slave operation lsb first or msb first data transfer four programmable bit rates end of transmission interrupt flag write collision flag protection wakeup from idle mode (slave mode only) figure 16. spi block diagram select spi clock (master) clock logic clock spi control spi status register 88 spi control register s m m s miso pb6 mosi pb5 sck pb7 ss pb4 pin control logic 8-bit shift register read data buffer divider 4 16 64 128 mstr spe msb lsb sysclk spr1 spr0 spif wcol spie spe dord mstr cpol cpha spr1 spr0 8 mstr spe dord s m spi interrupt request internal data bus
53 at43usb351m 3302e?usb?7/04 the interconnection between master and slave cpus with spi is shown in figure 17. the pb7(sck) pin is the clock output in the master mode and is the clock input in the slave mode. writing to the spi data register of the master cpu starts the spi clock generator, and the data written shifts out of the pb5(mosi) pin and into the pb5(mosi) pin of the slave cpu. after shifting one byte, the spi clock generator stops, setting the end of transmission flag (spif). if the spi interrupt enable bit (spie) in the spcr register is set, an interrupt is requested. the slave select input, pb4(ss), is set low to sele ct an individual slave sp i device. the two shift registers in the master and the slave can be considered as one distributed 16-bit circular shift register. this is shown in figure 17. when data is shifted from the master to the slave, data is also shifted in the opposite direction, simultaneously. this means that during one shift cycle, data in the master and the slave are interchanged. figure 17. spi master/slave interconnection the system is single buffered in the transmit direction and double buffered in the receive direc- tion. this means that bytes to be transmitted cannot be written to the spi data register before the entire shift cycle is completed. when re ceiving data, however, a received byte must be read from the spi data register before the next byte has been completely shifted in. other- wise, the first byte is lost. when the spi is enabled, the data direction of the mosi, miso, sck and ss pins is overrid- den according to the following table: note: see ?port b? on page 67. for a detailed descr iption of how to define the direction of the user defined spi pins. sck sck ss ss v cc miso miso mosi mosi lsb master msb 8-bit shift register spi clock generator lsb slave msb 8-bit shift register table 20. spi pin overrides pin direction, master spi direction, slave spi mosi user defined input miso input user defined sck user defined input ssn user defined input
54 at43usb351m 3302e?usb?7/04 ss pin functionality when the spi is configured as a master (mstr in spcr is set), the user can determine the direction of the ss pin. if ss is configured as an output, the pin is a general output pin which does not affect the spi system. if ss is configured as an input, it must be held high to ensure master spi operation. if the ss pin is driven low by peripheral circuitry when the spi is config- ured as master with the ss pin defined as an input, the spi system interprets this as another master selecting the spi as a slave and starting to send data to it. to avoid bus contention, the spi system takes the following actions: 1. the mstr bit in spcr is cleared and the spi system becomes a slave. as a result of the spi becoming a slave, the mosi and sck pins become inputs. 2. the spif flag in spsr is set, and if the spi interrupt is enabled and the i-bit in sreg are set, the interrupt ro utine will be executed. thus, when interrupt-driven spi transmittal is used in master mode, and there exists a possi- bility that ss is driven low, th e interrupt should a lways check that the mstr bit is still set. once the mstr bit has been cleared by a slave se lect, it must be set by the user to re-enable spi master mode. when the spi is configured as a slave, the ss pin is always input. when ss is held low, the spi is activated and miso becomes an output if co nfigured so by the user. all other pins are inputs. when ss is driven high, all pins are inputs, and the spi is passive, which means that it will not receive incoming data. note that the spi logic will be reset once the ss pin is brought high. if the ss pin is brought high during a tr ansmission, the spi will stop sending and receiv- ing immediately and both data received and data sent must be considered as lost. data modes there are four combinations of sck phase and polarity with respect to serial data, which are determined by control bits cpha and cpol. th e spi data transfer formats are shown in fig- ure 18 and figure 19. figure 18. spi transfer format wit h cpha = 0 and dord = 0 note: * not defined but normally lsb of character just received. * lsb 1 2 3 4 5 6 msb lsb 1 2 3 4 5 6 12345678 msb sck cycle # (for reference) sck (cpol = 0) sck (cpol = 1) mosi (from master) miso (from slave) ss (to slave)
55 at43usb351m 3302e?usb?7/04 figure 19. spi transfer format wit h cpha = 1 and dord = 0 note: * not defined, but normally lsb of previously transmitted character. 1 2 3 4 5 6 lsb 1 2 3 4 5 6 12345678 msb sck cycle # (for reference) sck (cpol = 0) sck (cpol = 1) mosi (from master) miso (from slave) ss (to slave) lsb msb *
56 at43usb351m 3302e?usb?7/04 spi control register ? spcr bit 7 ? spie: spi interrupt enable this bit causes the spi interrup t to be executed if spif bit in the spsr register is set and the global interrupts are enabled. bit 6 ? spe: spi enable when the spe bit is set (one), the spi is enabled. this bit must be set to enable any spi operations. bit 5 ? dord: data order when the dord bit is set (one), the lsb of the data word is transmitted first. when the dord bit is cleared (zero), the msb of the data word is transmitted first. bit 4 ? mstr: master/slave select this bit selects master spi mode when set (one), and slave spi mode when cleared (zero). if ss is configured as an input and is driven low while mstr is set, mstr will be cleared, and spif in spsr will become set. the user will th en have to set mstr to re-enable spi master mode. bit 3 ? cpol: clock polarity when this bit is set (one), sck is high when id le. when cpol is cleared (zero), sck is low when idle. refer to figure 18 and figure 19 for additional information. bit 2 ? cpha: clock phase refer to figure 18 or figure 19 for the functionality of this bit. bits 1,0 ? spr1, spr0: spi clock rate select 1 and 0 these two bits control the sck rate of the device configured as a master. spr1 and spr0 have no effect on the slave. t he relationship between sck and the oscillator clock frequency f cl is shown in the following table: bit 7 6 5 4 3 2 1 0 $0d ($2d) spie spe dord mstr cpol cpha spr1 spr0 spcr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 21. relationship between sck a nd the oscillator frequency spr1 spr0 sck frequency 00 3 mhz 0 1 750 khz 1 0 187.5 khz 1 1 93.75 khz
57 at43usb351m 3302e?usb?7/04 spi status register ? spsr bit 7 ? spif: spi interrupt flag when a serial transfer is complete, the spif bit is set (one) and an interrupt is generated if spie in spcr is set (one) and global interrupts are enabled. if ss is an input and is driven low when the spi is in master mode, this will also set the spif flag. spif is cleared by the hard- ware when executing the corresponding interrupt handling vector. alternatively, the spif bit is cleared by first reading the spi status register when spif is set (one), then accessing the spi data register (spdr). bit 6 ? wcol: write collision flag the wcol bit is set if the spi data register (spdr) is written during a data transfer. the wcol bit (and the spif bit) are cleared (zero) by first reading the spi status register when wcol is set (one), and then accessing the spi data register. bit 5..0 ? res: reserved bits these bits are reserved bits in the at 43usb351m and will always read as zero. spi data register ? spdr the spi data register is a read/write register used for data transfer between the register file and the spi shift register. writing to the register initiates data transmission. reading the regis- ter causes the shift register receive buffer to be read. bit76543210 $0e ($2e) spif wcol ? ? ? ? ? ? spsr read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 $0f ($2f) msb ? ? ? ? ? ? lsb spdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x undefined
58 at43usb351m 3302e?usb?7/04 analog-to-digital converter feature list: 10-bit resolution 4 lsb integral non-linearity 2 lsb absolute accuracy 12 ? 768 s conversion time up to 83 ksps at maximum resolution 12 multiplexed input channels rail-to-rail input range free running or single conversion mode interrupt on adc conversion complete the at43usb351m features a 10-bit successive approximation adc. the adc is connected to a 12-channel analog multiplexer to pins ad0 ? ad11. the adc contains a sample and hold amplifier that ensures that the input voltage to the adc is held at a constant level during conversion. a block diagram of the adc is shown in figure 20. the reference voltage of the adc is internally connected to the cexta voltage regulator. figure 20. analog-to-digital converter block schematic adc conversion complete irq 8-bit data bus adc multiplexer select (admux) prescaler adc ctrl and staus register (adcsr) adc data register (adch/adcl) conversion logic 10-bit dac + - sample and hold comparator 12-channel mux analog inputs 15 0 adif adie aden adsc adfr adif adie adps2 adps1 adps0 mux2 mux1 mux0 adc9..0 cexta
59 at43usb351m 3302e?usb?7/04 operation the adc converts an analog input voltage to a 10-bit digital value through successive approx- imation. the minimum value represents v ssa and the maximum value represents the voltage on the v ref pin minus one lsb. the analog input channel is selected by writing to the mux bits in admux. any of the twelve adc input pins adc11 ? 0 can be selected as single-ended inputs to the adc. the adc can operate in two modes ? single conversion and free running. in single conver- sion mode, each conversion will have to be initiated by the user. in free running mode, the adc is constantly sampling and updating the adc data register. the adfr bit in adcsr selects between the two available modes. the adc is enabled by setting the adc enable bit, aden in adcsr. input channel selections will not go into effect until aden is se t. the adc does not consume power when aden is cleared, so it is recommended to switch o ff the adc before entering power-saving sleep modes. a conversion is started by writing a logical "1" to the adc start conversion bit, adsc. this bit stays high as long as the conversion is in progress and will be set to zero by the hardware when the conversion is completed. if a different data channel is selected while a conversion is in progress, the adc will finish the current co nversion before performi ng the channel change. the adc generates a 10-bit result, which is presented in the adc data register, adch and adcl. when reading data, adcl must be read first, then adch, to ensure that the content of the data register belongs to the same conversion. once adcl is read, adc access to data register is blocked. this means that if adcl has been read and a conversion completes before adch is read, neither register is updated and the result from the conversion is lost. then adch is read, adc access to the adch and adcl register is re enabled. the adc has its own interrupt that can be triggered when a conversion completes. when adc access to the data registers is prohibited between reading of adch and adcl, the interrupt will trigger even if the result is lost. figure 21. adc prescaler adps0 adps1 adps2 aden ck ck/2 ck4 ck8 ck16 ck32 ck64 ck128 adc clock source 7-bit adc prescaler reset
60 at43usb351m 3302e?usb?7/04 the successive approximation circuitry requir es an input clock frequency between 15 khz and 1 mhz to achieve maximum resolution. if a resolu tion of lower than 10 bits is required, the input clock frequency to the adc can be higher than 200 khz to achieve a higher sampling rate. see "adc characteristics" for more deta ils. the adc module contains a prescaler, which divides the ck of 2 mhz clock input, to an acceptable adc clock frequency. the adps[0:2] bits in adcsr are used to generate a proper adc clock input frequency from 15.6 khz to 1.0 mhz. the prescaler starts counting from the moment the adc is switched on by setting the aden bit in adcsr. the prescaler keeps running for as long as the aden bit is set and is continuously reset when aden is low. when initiating a conversion by setting the adsc bit in adcsr, the conversion starts at the following rising edge of the adc clock cycle. a normal conversion takes 12 adc clock cycles. in certain situations, the adc needs more clock cycles for initialization and to minimize o ffset errors. extended conversions take 25 adc clock cycles and occur as the first conversion a fter the adc is switched on (aden in adcsr is set). the actual sample-and-hold takes place 1.5 adc clock cycles after the start of a conversion. when a conversion is complete, the result is written to the adc data registers and adif is set. in single conversion mode, adsc is cleared simultaneously. the software may then set adsc again and a new conversion will be initiate d on the first rising adc clock edge. in free running mode, a new c onversion will be starte d immediately after t he conversion completes, while adsc remains high. using free runni ng mode and an adc clock frequency of 1 mhz gives the lowest conversion time with a maximum resolution, 12 s, equivalent to 83 ksps. for a summary of conversion times, see table 22. figure 22. adc timing diagram, extended conversion (single conversion mode)
61 at43usb351m 3302e?usb?7/04 figure 23. adc timing diagram, single conversion figure 24. adc timing diagram, free running conversion table 22. adc conversion time condition sample and hold (cycles from start of conversion) conversion time (cycles) conversion time (s) normal conversion 12 10 12 - 768
62 at43usb351m 3302e?usb?7/04 adc multiplexer select register ? admux bits 7..3 ? res: reserved bits these bits are reserved bits in the at43usb351m and always read as zero. bits 3..0 ? mux3..mux0: analog channel select bits 3-0 the value of these three bits selects which analog input adc11..0 is connected to the adc. see table 23 for details. if these bits are changed during a conversion, the ch ange will not go into ef fect until this con- version is complete (a dif in adcsr is set). bit 7 6 5 4 3 2 1 0 $08 ($28) ? ? ? ? mux3 mux2 mux1 mux0 admux read/write r r r r r/w r/w r/w r/w initial value 0 0 n/a 0 0 0 0 0 table 23. input channel selections mux3.0 single-ended input 0000 adc0 0001 adc1 0010 adc2 0011 adc3 0100 adc4 0101 adc5 0110 adc6 0111 adc7 1000 adc8 1001 adc9 1010 adc10 1011 adc11 11xx adc0
63 at43usb351m 3302e?usb?7/04 adc control and status register ? adcsr bit 7 ? aden: adc enable writing a logical "1" to this bit enables the adc. by clearing this bit to zero, the adc is turned off. turning the adc off while a conversion is in progress will terminate this conversion. bit 6 ? adsc: adc start conversion in single conversion mode, a logical "1" must be written to this bit to start each conversion. in free running mode, a logical "1" must be written to this bit to start the first conversion. the first time adsc has been written after the adc has been enabled or if adsc is written at the same time as the adc is enabled, an extended conversion will precede the initiated conver- sion. this extended conversion performs initialization of the adc. adsc will read as one as long as a conversi on is in progress. when the conversion is com- plete, it returns to zero. when a extended conversion precedes a real conversion, adsc will stay high until the real conversion completes. writing a "0" to this bit has no effect. bit 5 ? adfr: adc free running select when this bit is set (one), the adc operates in free running mode. in this mode, the adc samples and updates the data registers continuously . clearing this bit (zero) will terminate free running mode. bit 4 ? adif: adc interrupt flag this bit is set (one) when an adc conversion completes and the data registers are updated. the adc conversion complete interrupt is execut ed if the adie bit and the i-bit in sreg are set (one). adif is cleared by the hardware wh en executing the corresponding interrupt han- dling vector. alternatively, adif is cleared by writing a logical "1" to the flag. beware that if doing a read-modify-write on adcsr, a pending interrupt can be disabled. this also applies if the sbi and cbi instructions are used. bit 3 ? adie: adc interrupt enable when this bit is set (one) and the i-bit in sreg is set (one), the adc conversion complete interrupt is activated. bits 2..0 ? adps2..adps0: adc pr escaler select bits these bits determine the division factor between the 12 mhz system clock frequency and the input clock to the adc. bit76543210 $07 ($27) aden adsc adfr adif adie adps2 adps1 adps0 adcsr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
64 at43usb351m 3302e?usb?7/04 adc data register ? adcl and adch when an adc conversion is complete, the result is found in these two registers. in free run mode, it is essential that both registers are read, and that adcl is read before adch. scanning multiple channels since change of analog channels is always delayed until a conv ersion is finished, the free run mode can be used to scan multiple channels without interrupting the converter. typically, the adc conversion complete interrupt will be used to perform the channel shift. however, the user should take the follo wing fact into consideration: the interrupt triggers once the result is ready to be read. in free run mode, the next conver- sion will start immediately when t he interrupt triggers. if admux is changed after the interrupt triggers, the next conversion has already started and the old setting is used. table 24. adc prescaler selections adps2 adps1 adps0 division factor 0002 0012 0104 0118 10016 10132 11064 111128 bit 7 6 5 4 3 2 1 0 $03 ($23) ? ? ? ? ? ? adc9 adc8 adch $24 ($44) adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 adcl read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0
65 at43usb351m 3302e?usb?7/04 adc characteristics i/o-ports all avr ports have true read-modify-write functionality when used as general digital i/o ports. this means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the sbi and cbi instructions. the same applies for changing drive value if configured as output or enabling/disabling of pull-up resistors if config- ured as input. port a port a is an 8-bit bi-directional i/o port. the port a output buffers can sink or source 2 ma. three i/o memory address locations are allocated for the port a, one each for the data regis- ter porta, $1b($3b), data direction register (ddra), $1a($3a) and the port a input pins (pina) $19($39). the port a input pins address is read only, while the data register and the data direction register are read/write. all port pins have individually selectable pull-up resistors. when pins pa0 to pa7 are used as inputs and are externally pulled lo w, they will source current if th e internal pull-up resistors are activated. symbol parameter condition min typ max unit s resolution 10 bits integral non-linearity v ref = vcexta 4 lsb differential non-linearity v ref = vcexta 4 lsb zero error (offset) -2 2 lsb full scale error -4 4 lsb v ref input resistance 25 c121824k ? analog input resistance 100 m ? conversion time 12 768 s clock frequency at 50% duty cycle 1 mhz
66 at43usb351m 3302e?usb?7/04 port a data register ? porta port a data direction register ? ddra port a input pins address ? pina the port a input pins address (pina) is not a register, and this address enables access to the physical value on each port a pin. when reading porta the port a data latch is read, and when reading pina, the logical values present on the pins are read. porta as general digital i/o all 8 pins in port a have equal function ality when used as digital i/o pins. pan, general i/o pin: the ddan bit in the ddra register se lects the direction of this pin, if ddan is set (one), pan is configured as an output pin. if ddan is cleared (zero), pan is config- ured as an input pin. if portan is set (one) when the pin is configured as an input pin, the mos pull-up resistor is activated. to switch the pull-up resistor off, the portan has to be cleared (zero) or the pin has to configured as an output pin. the port a pins are tri-stated when a reset condition becomes active , even if the clock is not active. note: n: 7, 6...0, pin number. bit 7 6 5 4 3 2 1 0 $1b ($3b) porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 porta read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 $1a ($3a) dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 ddra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7654 3 210 $19 ($39) pina7 pina6 pina5 pina4 pin a3 pina2 pina1 pina0 pina read/write r r r r r r r r initial value n/a n/a n /a n/a n/a n/a n/a n/a table 25. ddan effects on port a pins ddan portan i/o comment 0 0 input tri-state (hi-z) 0 1 input pan will source current if ext. pulled low. 1 0 output push-pull zero output 1 1 output push-pull one output
67 at43usb351m 3302e?usb?7/04 port b port b is a 4-bit bi-directional i/o port. the port b output buffers can sink or source 2 ma. three i/o memory address locations are allocated for the port b, one each for the data regis- ter - portb, $18($38), data direction register (ddrb), $17($37) and the port b input pins (pinb), $16($36). the port b input pins address is read only, while the data register and the data direction register are read/write. all port pins have individually selectable pull-up resistors. when pins pb0 to pb7 are used as inputs and are externally pulled lo w, they will source current if th e internal pull-up resistors are activated the port b pins with alternate functi ons are shown in the following table: when the pins are used for the alternate function the ddrb and portb register has to be set according to the alternate function description. table 26. port b pins alternate functions port pin alternate functions pb4 ss (spi slave select input) pb5 mosi (spi bus master output/slave input) pb6 miso (spi bus master input/slave output) pb7 sck (spi bus serial clock)
68 at43usb351m 3302e?usb?7/04 port b data register ? portb port b data direction register ? ddrb port b input pins address ? pinb the port b input pins address (pinb) is not a register, and this address enables access to the physical value on each port b pin. when reading portb, the port b data latch is read, and when reading pinb, the logical values present on the pins are read. portb as general digital i/o all 8 pins in port b have equal functi onality when used as digital i/o pins. pbn, general i/o pin: the ddbn bit in the ddrb register se lects the direction of this pin, if ddbn is set (one), pbn is con-figured as an output pin. if ddbn is cleared (zero), pbn is con- figured as an input pin. if portbn is set (one) when the pin is configured as an input pin, the mos pull-up resistor is activated. to switch the pull-up resistor off, the portbn has to be cleared (zero) or the pin has to configured as an output pin. the port b pins are tri-stated when a reset condition becomes active , even if the clock is not active. note: n: 7, 6...0, pin number. bit 7 6 5 4 3 2 1 0 $18 ($38) portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 portb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 $17 ($37) ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 $16 ($36) pinb7 pinb6 pinb5 pinb4 pi nb3 pinb2 pinb1 pinb0 pinb read/write r r r r r r r r initial value n/a n/a n/a n/a n/a n/a n/a n/a table 27. ddbn effects on port b pins ddbn portbn i/o comment 0 0 input tri-state (hi-z) 0 1 input pbn will source current if ext. pulled low. 1 0 output push-pull zero output 1 1 output push-pull one output
69 at43usb351m 3302e?usb?7/04 port d port d is a 7-bit bi-directional i/o port. its output buffers can sink or source 2 ma. three i/o memory address locations are allocated for the port d, one each for the data regis- ter - portd, $12($32), data direction register (ddrd), $11($31) and the port d input pins (pind), $10($30). the port d input pins address is read only, while the data register and the data direction register are read/write. all port pins have individually selectable pull-up resistors. when pins pd0 to pd7 are used as inputs and are externally pulled lo w, they will source current if th e internal pull-up resistors are activated some port d pins have alternate functions as shown in table 28. when the pins are used for the alternate functi on the ddrd and portd register has to be set according to the alternate function description. port d data register ? portd port d data direction register ? ddrd port d input pins address ? pind the port d input pins address (pind) is not a register, and this address enables access to the physical value on each port d pin. when readin g portd, the port d data latch is read, and when reading pind, the logical values present on the pins are read. table 28. port d alternate functions port pin alternate function pd2 int0, external interrupt 0 pd3 int1, external interrupt 1 pd4 icp, timer/counter 1 input capture pd5 oc1a timer/counter1 output compare a pd6 oc1b timer/counter1 output compare b bit 7 6 5 4 3 2 1 0 $12 ($32) portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 portd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7654 3 210 $11 ($31) ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 ddrd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 $10 ($30) pind7 pind6 pind5 pind4 pind 3 pind2 pind1 pind0 pind read/write r r r r r r r r initial value n/a n/a n/a n/a n/a n/a n/a n/a
70 at43usb351m 3302e?usb?7/04 portd as general digital i/o pdn, general i/o pin: the dddn bit in the ddrd register selects the direction of this pin. if dddn is set (one), pdn is con-figured as an outp ut pin. if dddn is cleared (zero), pdn is con- figured as an input pin. if portdn is set (one) when the pin is configured as an input pin, the mos pull-up resistor is activated. to switch the pull-up resistor off, the portdn has to be cleared (zero) or the pin has to configured as an output pin. the port d pins are tri-stated when a reset condition becomes active , even if the clock is not active. note: n: 7, 6...0, pin number. table 29. dddn bits on port d pins dddn portdn i/o comment 0 0 input tri-state (hi-z) 0 1 input pdn will source current if ext. pulled low. 1 0 output push-pull zero output 1 1 output push-pull one output
71 at43usb351m 3302e?usb?7/04 programming the usb module the usb hardware consists of a usb function with its address and endpoints. its operation is controlled through a set of memory mapped registers. the exact configuration of the usb device is defined by the software. the usb function has one control endpoint and 4 program- mable endpoints. all the endpoints have their own fifo. function endpoints 1 and 2 fifos are 64 bytes deep and function endpoints 3 and 4 have 8-byte fifos. the usb function the usb function hardware is designed to op erate in the single packet mode and to manage the usb protocol layer. it consists of a serial interface engine (sie), endpoint fifos and a function interface unit (fiu). the sie perfo rms the following tasks: usb signaling detec- tion/generation, data serialization/de-serializatio n, data encoding/decoding, bit stuffing and un- stuffing, clock/data separatio n, and crc generation/checking. it also decodes and manages all packet data types and packet fields. the endpoint fifo buffers the data to be sent out or data received. the fiu manages the flow of data between the sie, fifo and the internal microcontroller bus. it controls the fifo and monitors the status of the transactions and inte rfaces to the cpu. it initiates interrupts and acts upon commands sent by the firmware. the usb function hardware of the at43usb351m makes the physical interface and the proto- col layer transparent to the user. to start the process, the firmware must first enable the endpoints and which place them in receive mode by default. the device address by default is address 0. the usb function hardware then waits for a setup token from the host. when a valid the setup token is received, it automatically stores the data packet in endpoint 0 fifo and responds with an ack. it then notifies the microcontroller through an interrupt. the micro- controller reads the fifo and parses the request. transactions for the non-control endpoints are ev en simpler. once the endpoint is enabled, it waits for an in or an out token depending whether it is programmed as an in or out end- point. for example, if it is an in endpoint, the microcontroller simply loads the data into the endpoint's fifo and sets a bit in the control and status register. the usb hardware will assemble the data in a usb packet and waits for an in token. when it receives one, it auto- matically responds by transmitting the data packet and completes the transaction by waiting for the host's ack. when one is received, the usb hardware will signal the microcontroller that the transaction has been completed successfully. retries and data toggles are performed automatically by the usb hardware. when the in endpoint is not ready to send data, in the case where the microcontroller has not filled the fifo, it will automatically respond with a nak. similarly, an out endpoint will wait for an out to ken. when one is received, it will store the data in the fifo, completes the transaction and interrupt the microcontroller, which then reads the fifo and enables the endpoint for the next packet. if the fifo is not cleared, the usb hardware will resp onds with a nak. a detailed description of how usb transactions are handled is described in the following sec- tions. first for a control endpoint and then for non-control endpoints.
72 at43usb351m 3302e?usb?7/04 control transfers at control endpoint ep0 the description given below is for the function control endpoint, but applies to the hub control endpoint as well if the proper registers are used. the following illustration describ es the three possible types of control transfers ? control write, control read and no-data control: the following state diagram shows how the vari ous state transitions are triggered. additional decision making may take place within the response states to determine the next expected state. unmarked arcs represent transitions that trigger immediately following completion of the response state processing. stable states, those requiring an interrupt to exit having no unmarked arcs as exit paths, are shown in bold. setup data status stage stage stage control write data0 data1 data0 data0/1 data1(0) control read data0 data1 data0 data0/1 data1(0) setup status stage stage no-data control data0 data1(0) setup(0) setup(0) out(1) out(0) out(0/1) ? in(1) in(1) setup(0) in(1) in(1) out(1) in(0) in(0/1) ? legend: datan data packet with pid?s data toggle bit equal to n data1(0) zero length data1 packet idle setup response no-data status response control read status response control write status response rx_setup_int rx_out_int tx_complete_int tx_complete_int tx_complete_int rx_out_int control read data response tx_complete_int control write data response rx_out_int ( any stable state )
73 at43usb351m 3302e?usb?7/04 the following information descr ibes how the at43usb351m?s usb hardware and firmware operates during a control transfer between the host and the function?s control endpoint. idle state this is the default state from power-up. setup response state the function interface unit (fiu) receives a setup token with 8 bytes of data from the host. the fiu stores the data in the fifo, sends an ack back to the host and asserts an rx_setup interrupt. legend: data1/data0 = data packet with data1 or data2 pid data1(0) = zero length data1 packet hardware firmware 1. setup token, data from host 2. ack to host 3. store data in fifo 4. set rx setup int 5. read uisr 6. read csr0 7. read byte count 8. read fifo 9. parse command data 10. write to h/fcar0: a. if control read: set dir, clear rx setup, fill fifo, set tx packet ready in car0 b. if control write: clear dir in car0 c. if no data stage: set data end, clear dir, set force stall in car0 11. set uiar[ep0 intack] to clear the interrupt source
74 at43usb351m 3302e?usb?7/04 no-data status response state the function interface unit receives an in to ken from the host. the fiu responds with a zero length data1 packet until receiving an ack from the host, then asserts a tx_complete interrupt. control read data response state the function interface unit receives an in to ken from the host. the fiu responds with naks until tx_packet_ready is set. the fiu then sends the data in the fifo upstream, retrying until it successfully receives an ack from the host. finally, the fiu clears the tx_packet_ready bit and assert s a tx_complete interrupt. hardware firmware 1. in token from host 2. send data1(0) 3. ack from host 4. set tx complete int 5. read uisr 6. read csr0 7. if set address, program the new address, set add_en bit 8. clear tx_complete, clear data end, set force stall in car0 9. set uiar[ep0 intack] hardware firmware 1. in token from host 2. a. if tx packet ready = 1, send data 0 / data 1 b. if tx packet ready = 0, send nak 3. ack from host 4. clear tx packet ready set tx complete int 5. read uisr 6. read csr0 7. clear tx complete in car0: a. if more data: fill fifo, set tx packet ready, set dir in car0 b. if no more data: set force stall, set data end in car0 8. set uiar[ep0 intack] to clear interrupt source repeat steps 1 through 8
75 at43usb351m 3302e?usb?7/04 control read status response state the function interface unit receives an out token from the host with a zero length data1 packet. the fiu responds with a nak until tx_c omplete is cleared. the fiu will then ack the retried out token from the host and assert an rx_out interrupt. control write data response state the function interface unit receives an out token from the host with a data packet. the fiu places the incoming data into the fifo, issues an ack to the host, and asserts an rx_out interrupt. hardware firmware 1. out token from host 2. data1(0) from host 3. tx complete = 0 ? a. if yes, ack to host set rx out int b. if no, nak to host 4. read uisr 5. read csr0 6. clear rx out, set data end, set force stall in h/fcar0. note: a setup token will clear data end, therefore, it is not cleared by fw in case host retries. 7. set uiar[ep0 intack] to clear interrupt source hardware firmware 1. out token from host 2. put data0/data1 into fifo 3. ack to host 4. set rx out int 5. read uisr 6. read csr0 7. read fifo 8. clear rx out if last data packet, set force stall, set data end. 9. set uiar[ep0 intack] to clear the interrupt source repeat steps 1 through 9 until last data packet:
76 at43usb351m 3302e?usb?7/04 control write status response state the function interface unit receives an in to ken from the host. the fiu responds with a zero length data1 packet, retrying until it rece ives an ack back from the host. the fiu then asserts a tx_com plete interrupt. hardware firmware 1. in token from host 2. send data1(0) 3. ack from host 4. set tx complete int 5. read uisr 6. read csr0 7. clear tx complete, clear data end, set force stall in car0 8. set uiar[ep0 intack] to clear the interrupt source
77 at43usb351m 3302e?usb?7/04 interrupt/bulk in transfers at function endpoint ep1, 2, 3 and 4 the firmware must first condition the endpoint through the endpoint control register, fendp1/2/3/4_cntr: set endpoint direction: set epdir set interrupt or bulk: eptype = 11 or 10 enable endpoint: set epen the function interface unit receives an in to ken from the host. the fiu responds with naks until tx_packet_ready is set. the fiu then sends the data in the fifo upstream, retrying until it successfully receives an ack from the host. finally, the fiu clears the tx_packet_ready bit and assert s a tx_complete interrupt. 1. read uisr 2. read fcsr1/2/3/4 3. clear tx_complete if more data: fill fi fo, set tx packet ready wait for tx_complete interrupt if no more data: set data end in fcar1/2/3/4 4. set uiar[fep1/2/3/4 intack] to clear the interrupt source interrupt/bulk out transfers at function endpoint ep1, 2, 3 and 4 the firmware must first condition the endpoint through the endpoint control register, fendp1/2/3/4_cntr: set endpoint direction: clear epdir set interrupt or bulk: eptype = 11 or 10 enable endpoint: set epen the function interface unit receives an out token from the host with a data packet. the fiu places the incoming data into the fifo, issues an ack to the host, and asserts an rx_out interrupt. 1. read uisr 2. read fcsr1/2/3/4 3. read fifo 4. clear rx_out if more data: wait for rx_out interrupt if no more data: set data end 5. set uiar[fep1/2/3/4 intack] to clear the interrupt source
78 at43usb351m 3302e?usb?7/04 usb registers the following sections describe the registers of the at43usb351m?s function unit. reading a bit for which the microcontroller does not have read access will yield a zero value result. writing to a bit for which the microcontroller does not have write access has no effect. hub address register ? haddr this register is an artifact of the at43usb 355. it is included in the at43usb351m to make the two devices binary-compatible. in th e at43usb351m only bit 7 is meaningful. hub address register ? haddr bit 7 ? saen: single address enable in the at43usb351m, this bit should be set to ?1?. bit 6..0 ? hadd6...0: hub address[6:0] these bits are don?t cares in the at43usb351m. bit 7 6 5 4 3 2 1 0 $1fef saen hadd6 hadd5 hadd4 hadd3 hadd2 hadd1 hadd0 haddr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
79 at43usb351m 3302e?usb?7/04 function address register ? faddr the usb function contains an address register th at contains the function address assigned by the host. this function address register must be programmed by the microcontroller once it has received a set_address request from the host and complete d the status phase of the transaction. after power up or reset, this register will contain the value of 0x00. function address register ? faddr bit 7 ? fen: function enable the function enable bit (fen) allows the firmware to enable or disable the function endpoints. the firmware will set this bit after receipt of a reset through the hub, setportfea- ture[port_reset]. once this bit is set, the usb hardware pa sses to and fr om the host. when the single address bit is set, the condition of fen is ignored. bit 6..0 ? fadd6...0: function address[6:0] endpoint registers function endpoint 0 control register ? fendp0_cr bit 7 ? epen: endpoint enable 0 = disable endpoint 1 = enable endpoint bit 6..4 ? reserved these bits are reserved in the at43usb351m and will read as zero. bit 3 ? dtgle: data toggle identifies data0 or data1 packets. this bit w ill automatically toggle and requires clearing by the firmware only in certain special circumstances. bit 2 ? epdir: endpoint direction 0 = out 1 = in bit 1, 0 ? eptype: endpoint type these bits must be programmed as 0, 0. bit76543210 $1fee fen fadd6 fadd5 fadd4 fadd3 fadd2 fadd1 fadd0 faddr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 765432 1 0 $1fe5 epen ? ? ? dtgle epdir eptype1 eptype0 fendp0_cr read/write r/w r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
80 at43usb351m 3302e?usb?7/04 function endpoint 1..4 control register ? fendp1..4_cr bit 7 ? epen: endpoint enable 0 = disable endpoint 1 = enable endpoint bit 6..4 ? reserved these bits are reserved in the at43usb351m and will read as zero. bit 3 ? dtgle: data toggle identifies data0 or data1 packets. this bit w ill automatically toggle and requires clearing by the firmware only in certain special circumstances. bit 2 ? epdir: endpoint direction 0 = out 1 = in bit 1, 0 ? eptype: endpoint type these bits programs the type of endpoint. bit 7 6 5 4 3 2 1 0 $1fe4 epen ? ? ? dtgle epdir eptype1 eptype0 fendp1_cr $1fe3 epen ? ? ? dtgle epdir eptype1 eptype0 fendp2_cr $1fe2 epen ? ? ? dtgle epdir eptype1 eptype0 fendp3_cr $1fe6 epen ? ? ? dtgle epdir eptype1 eptype0 fendp4_cr read/write r/w r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit1 bit0 type 0 1 isochronous 10bulk 1 1 interrupt
81 at43usb351m 3302e?usb?7/04 function endpoint 0..4 data register ? fdr0..4 these registers are used to read data from or to write data to the function endpoint 0 fifos. bit 7..0 ? fdat7..0: fifo data function endpoint 0..4 byte count register ? fbyte_cnt0..4 the contents of these registers stores the number of bytes to be sent or that was received by function endpoints. this count includes the 16-bit crc. to get the actual byte count of the data, subtract the count in the register by 2. the functions ep3 and ep4 have 8-byte fifos while function ep1 and ep2 have 64-byte fifos. bit 7 ? reserved this bit is reserved in the at 43usb351m and will read as zero. bit 6..0 ? bytct6..0: byte count ? length of endpoint data packet bit 7 6 5 4 3 2 1 0 $1fd6 data7 data6 data5 data4 data3 data2 data1 data0 fdr4 $1fd5 data7 data6 data5 data4 data3 data2 data1 data0 fdr0 $1fd4 data7 data6 data5 data4 data3 data2 data1 data0 fdr1 $1fd3 data7 data6 data5 data4 data3 data2 data1 data0 fdr2 $1fd2 data7 data6 data5 data4 data3 data2 data1 data0 fdr3 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543 210 function ep4 $1fce ? ? bytct5 bytct4 bytct3 bytct2 bytct1 bytct0 fbyte_cnt4 function ep0 $1fcd ? ? bytct5 bytct4 bytct3 bytct2 bytct1 bytct0 fbyte_cnt0 function ep1 $1fcc ? bytct6 bytct5 bytct4 bytct3 bytct2 bytct1 bytct0 fbyte_cnt1 function ep2 $1fcb ? bytct6 bytct5 bytct4 bytct3 bytct2 bytct1 bytct0 fbyte_cnt2 function ep3 $1fca ? ? bytct5 bytct4 bytct3 bytct2 bytct1 bytct0 fbyte_cnt3 read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
82 at43usb351m 3302e?usb?7/04 function endpoint 0 service routine register ? fcsr0 bit 7..4 ? reserved these bits are reserved in the at43usb351m and will read as zero. bit 3 ? stall sent the usb hardware sets this bit after a stall has been sent to the host. the firmware uses this bit when responding to a get status[endpoint] request. it is a read only bit and that is cleared indirectly by writing a one to the stall_sent_ack bit of the control and acknowl- edge register. bit 2 ? rx setup: setup packet received this bit is used by control endpoints only to si gnal to the microcontroller that the usb hard- ware has received a valid setup packet and that the data portion of the packet is stored in the fifo. the hardware will clear a ll other bits in this register while setting rx setup. if inter- rupt is enabled, the microcontroller will be interrupted when rx setup is set. after the completion of reading the data from the fifo, firmware should clear this bit by writing a one to the rx_setup_ack bit of the control and acknowledge register. bit 1 ? rx out packet the usb hardware sets this bit after it has stored the data of an out transaction in the fifo. while this bit is set, the hardware will nak a ll out tokens. the usb ha rdware will not over- write the data in the fifo except for an early set-up. rx out packet is used for the following operations: 1. control write transacti ons by a control endpoint. 2. out transaction with data1 pid to complete the status phase of a control endpoint. setting this bit causes an interrupt to the micr ocontroller if the interrupt is enabled. fw clears this bit after the fifo contents have been read by writing a one to the rx_out_packet_ack bit of the control and acknowledge register. bit 0 ? tx compl: transmit completed this bit is used by a control endpoint hardware to signal to the microcontroller that it has suc- cessfully completed certain tr ansactions. tx complete is set at the completion of a: 1. control read data stage. 2. status stage without data stage. 3. status stage after a control write transaction. this bit is read only and is cl eared indirectly by writing a one to the tx_complete_ack bit of the control and acknowledge register. bit 7 6 5 4 3 2 1 0 function ep0 $1fdd ? ? ? ? stall sent rx setup rx out packet tx complete fcsr0 read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0
83 at43usb351m 3302e?usb?7/04 function endpoint 0 control and acknowledge register ? fcar0 bit 7 ? dir: control transfer direction it is set by the microcontroller firmware to indicate the direction of a control transfer to the usb hardware. the fw writes to this bit location after it receives an rx setup interrupt. the hard- ware uses this bit to determine the status phase of a control transfer. 0 = control write or no data stage 1 = control read bit 6 ? data end when set to 1 by firmware, this bit indicate that the microcontroller has either placed the last data packet in fifo, or that the microcontrolle r has processed the last data packet it expects from the host. this bit is used by control endp oints only together with bit 4 (tx packet ready) to signal the usb hardware to go to the stat us phase after the packet currently residing in the fifo is transmitted. after the hardware completes the status phase it will interrupt the microcontroller without clearing this bit. bit 5 ? force stall this bit is set by the microcontroller to indi cate a stalled endpoint. the hardware will send a stall handshake as a response to the next in or out token, or whenever there is a control transfer without a data stage. the microcontroller sets this bit if it wants to force a stall. a stall is sent if any of the fol- lowing condition is encountered: 1. an unsupported request is received. 2. the host continues to ask for data after the data is exhausted. 3. the control transfer has no data stage. bit 4 ? tx packet ready: transmit packet ready when set by the firmware, this bit indicates that the microcontroller has loaded the fifo with a packet of data. this bit is cleared by the hardware after the usb host acknowledges the packet. for iso endpoints, this bit is clear ed unconditionally after the data is sent. this bit is used for the following operations: 1. control read transactions by a control endpoint. 2. in transactions with data1 pid to complete the status phase for a control endpoint, when this bit is zero but data end set high (bit 4). 3. by a bulk in or iso in or int in endpoint. the microcontroller should write in to the fifo only if this bit is cleared. after it has completed writing the data, it should set this bit. this data can be of zero length. hardware clears this bit after it receives an ack. if the interrupt is enabled and if the tx com- plete bit is set, clearing the tx packet ready bit by the hardware causes an interrupt to the microcontroller. bit 3 ? stall_sent_ack: acknowledge stall sent interrupt bit 7 6 5 4 3 2 1 0 function ep0 $1fdd dir data end force stall tx packet ready stall_ sent_ ack rx_ setup_ ack rx_out_ packet_ ack tx_ complete_ ack fcar0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
84 at43usb351m 3302e?usb?7/04 firmware sets this bit to clear stall sent, csr bit 3. the 1 written in the csrack3 bit is not actually stored and thus does not have to be cleared. bit 2 ? rx_setup_ack: acknowledge rx setup interrupt firmware sets this bit to clear rx setup, csr bit2. the 1 written in the csrack2 bit is not actually stored and thus does not have to be cleared. bit 1 ? rx_out_packet_ack: acknowledge rx out packet interrupt firmware sets this bit to clear rx out pac ket, csr bit1. the 1 written in the csrack1 bit is not actually stored and thus does not have to be cleared. bit 0 ? tx_complete_ack: acknowle dge tx complete interrupt firmware sets this bit to clear tx complete , csr bit0. the 1 written in the csrack0 bit is not actually stored and thus does not have to be cleared. function endpoint 0..4 service routine register ? fcsr0..4 bit 7..4 ? reserved these bits are reserved in the at43usb351m and will read as zero. bit 3 ? stall sent the usb hardware sets this bit after a stall has been sent to the host. the firmware uses this bit when responding to a get status[endpoint] request. it is a read only bit and that is cleared indirectly by writing a one to the stall_sent_ack bit of the control and acknowl- edge register. bit 2 ? reserved this bit is reserved in the at 43usb351m and will read as zero. bit 1 ? rx out packet the usb hardware sets this bit after it has stored the data of an out transaction in the fifo. while this bit is set, the hardware will nak a ll out tokens. the usb ha rdware will not over- write the data in the fifo except for an early set-up. rx out packet is used by a bulk out or iso out or int out endpoint. setting this bit causes an interrupt to the micr ocontroller if the interrupt is enabled. fw clears this bit after the fifo contents have been read by writing a one to the rx_setup_ack bit of the control and acknowledge register. bit 0 ? tx complete: transmit completed this bit is used by the endpoint hardware to si gnal to the microcontroller that the in transac- tion was completed su ccessfully. this bit is read only and is cleared indirectly by writing a one to the tx_complete_ack bit of the control and acknowledge register. bit 7654 3 2 1 0 function ep1 $1fdc ? ? ? ? stall sent ? rx out packet tx complete fcsr1 function ep2 $1fdb ? ? ? ? stall sent ? rx out packet tx complete fcsr2 function ep3 $1fda ? ? ? ? stall sent ? rx out packet tx complete fcsr3 function ep4 $1fde ? ? ? ? stall sent ? rx out packet tx complete fcsr4 read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0
85 at43usb351m 3302e?usb?7/04 function endpoint 0..4 control and acknowledge register ? fcar0..4 bit 7 ? reserved this bit is reserved in the at 43usb351m and will read as zero. bit 6 ? data end when set to 1 by firmware, this bit indicate that the microcontroller has either placed the last data packet in fifo, or that the microcontrolle r has processed the last data packet it expects from the host. bit 5 ? force stall this bit is set by the microcontroller to indi cate a stalled endpoint. the hardware will send a stall handshake as a response to the next in or out token. the microcontroller sets this bit if it wants to force a stall. a stall is send if the host continues to ask for data after the data is exhausted. bit 4 ? tx packet rdy: transmit packet ready when set by the firmware, this bit indicates that the microcontroller has loaded the fifo with a packet of data. this bit is cleared by the hardware after the usb host acknowledges the packet. for iso endpoints, this bit is clear ed unconditionally after the data is sent. the microcontroller should write in to the fifo only if this bit is cleared. after it has completed writing the data, it should set this bit. this data can be of zero length. the hardware clears this bit after it receives an ack. if the interrupt is enabled and if the tx complete bit is set, clearing the tx packet ready bit by the hardware causes an interrupt to the microcontroller. bit 3 ? stall_sent_ack: acknowledge stall sent interrupt firmware sets this bit to clear stall sent, csr bit 3. the 1 written in the csrack3 bit is not actually stored and thus does not have to be cleared. bit 2 ? reserved this bit is reserved in the at 43usb351m and will read as zero. bit 1 ? rx_out_packet_ack: acknowledge rx out packet interrupt firmware sets this bit to clear rx out pac ket, csr bit1. the 1 written in the csrack1 bit is not actually stored and thus does not have to be cleared. bit 0 ? tx_complete_ack: acknowledge tx complete interrupt firmware sets this bit to clear tx complete , csr bit0. the 1 written in the csrack0 bit is not actually stored and thus does not have to be cleared. bit 7 6 5 4 3 2 1 0 function ep1 $1fa4 ? data end force stall tx packet rdy stall_sent- ack ? rx_out_packet _ack tx_complete _ack fcar1 function ep2 $1fa3 ? data end force stall tx packet rdy stall_sent- ack ? rx_out_packet _ack tx_complete -ack fcar2 function ep3 $1fa2 ? data end force stall tx packet rdy stall_sent- ack ? rx_out_packet _ack tx_complete -ack fcar3 function ep4 $1fa6 ? data end force stall tx packet rdy stall_sent- ack ? rx_out_packet _ack tx_complete -ack fcar4 read/write r r/w r/w r/w r/w r r/w r/w initial value 0 0 0 0 0 0 0 0
86 at43usb351m 3302e?usb?7/04 hub general registers global state register ? glb_state bit 7...5 ? reserved bits these bits are reserved in the at43usb351m and will read as zeros. bit 4 ? susp flg: suspend flag this bit is set to 1 while the usb hardware is in the suspended state. this bit is a firmware read only bit. it is set and cleared by the usb hardware. bit 3 ? resume flgl resume flag when the usb hardware receives a resume signal from the upstream device it sets this bit. this bit will stay set until the usb hardware co mpletes the downstream resume signaling. this bit is a firmware read only bit. it is set and cleared by the usb hardware. bit 2 ? reserved this bit is reserved in the at 43usb351m and will read as zero. bit 1 ? confg: configured this bit is set by firmware after a valid set_configuration request is received. it is cleared by a reset or by a set_configuration with a value of 0. bit 0 ? hadd en: hub address enabled this bit is set by firmware after the stat us phase of a set_address request transaction so the hub will use the new address starting at the next transaction. bit 7 6 5 4 3 2 1 0 $1ffb ? ? ? susp flg resume flg ? confg hadd en glb_state read/write r r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0
87 at43usb351m 3302e?usb?7/04 suspend and resume the at43usb351m enters suspend only when r equested by the usb host through bus inac- tivity for at least 3 ms. the usb hardware woul d detect this request, sets the glb_susp bit of sprsr, suspend/resume register, and interrupts the microcontroller if the interrupt is enabled. the microcontroller should shut down any peripheral activity and enter the power down mode by setting the se and sm bits of mcucr and then executes the sleep instruc- tion. the usb hardware shuts o ff the oscillator and pll. oper ation is resumed when a non- idle signal is reserved or an external interrupt is detected. remote wakeup while the at43usb351m is in global suspend, resume signaling is also possible through remote wakeup if the remote wakeup feature is enabled. remote wakeup is defined as an external interrupt. a remote wakeup is initiated thro ugh int0 or the external interrupt, int1, which enables the oscillator/pll and the usb hard ware. the usb hardware drives resume signaling and sets the frmwup and rsm bits of sprsr which generates an interrupt to the microcontroller. the microcontroller starts executing where it left off and services the interrupt. as part of the isr, the firmware clears the glb susp bit. instead of int0 and int1, remote wakeup is al so triggered through the pd0 pin. this mode is enabled by setting bit 2 of uovcer (overcurrent detect register) and when a pull-up resistor of at least 10 k ? is connected to pd0. whenever pd0 is pulled low during suspend, a resume is triggered. suspend and resume process suspend the host stops sending packets, the hardwa re detects this as sus pend signaling. the hard- ware asserts the gl b_susp interrupt. hardware firmware 1.host stops sending packets 2. suspend signaling detected 3. set gbl sus bit interrupt 4. shut down any peripheral activity 5. set sleep enable and sleep mode bits of mcucr 6. set gpio to low power state if required 7. set uovcer bit 2 (optional) 8. execute sleep instruction 9. sleep bit detected 10. shut off oscillator
88 at43usb351m 3302e?usb?7/04 resume the host resumes signaling, the hardware detects this as resume. the hardware enables the oscillator and asserts the rsm interrupt. remote wake-up, function the hardware detects an int0/int1 or pd0 if enabled, and starts resume signaling upstream. finally, the hardware enables the oscillator and asserts the rsm and frwup interrupts. hardware firmware 1.host resumes signaling 2. resume signaling detected 3. enable oscillator 4. set rsm bit interrupt 5. reset rsm and gbl susp bits 6. restore gpio states if required 7. clear uovcer bit 2 (if set when enter- ing suspend) 8. enable peripheral activity hardware firmware 1.external event activates int0/int1/pd0 2. initiate resume signaling 3. enable oscillator 4. set rsm and frmwup bits interrupt 5. clear glb susp, rsm, frmwup bits 6. restore gpio states if required 7. clear uovcer bit 2 (if used) 8. enable peripheral activity
89 at43usb351m 3302e?usb?7/04 electrical specification absolute maximum ratings stresses beyond those listed below may cause permanent damage to the device. this is a stress rating only and functional operation of t he device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. expo- sure to absolute maxi mum rating conditions for extended pe riods may affect device reliability. note: vcext is the voltage of cext1, cext2 or cexta. dc characteristics the values shown in this table are valid for ta = 0 c to 85 c, vcc = 4.4 to 5.25v, unless oth- erwise noted. table 30. absolute maximum ratings symbol parameter condition min max unit v cc5 5v power supply 5.5 v vi dc input voltage -0.3v vcext +0.3 4.6 max v vo dc output voltage -0.3 vcext +0.3 4.6 max v to operating temperature -40 +125 c ts storage temperature -65 +150 c table 31. power supply symbol parameter condition min max unit v cc 5v power supply 4.4 5.25 v i cc 5v supply current 30 ma i ccs suspended device current 300 ua
90 at43usb351m 3302e?usb?7/04 note: vcext is the voltage of cext1, cext2 or cexta. note: xtal2 must not be used to drive other circuitry. table 32. usb signals: dpx, dmx symbol parameter condition min max unit v ih input level high (driven) 2.0 v v ihz input level high (floating) 2.7 v v il input level low 0.8 v v di differential input sensitivity dpx and dmx 0.2 v v cm differential common mode range 0.8 2.5 v v ol1 static output low rl of 1.5 k ? to 3.6v 0.3 v v oh1 static output 0high rl of 15 k ? to gnd 2.8 3.6 v v crs output signal crossover 1.3 2.0 v v in input capacitance 20 pf table 33. pa, pb, pd symbol parameter condition min max unit v ol2 output low level, pa, pb, pd iol = 2 ma 0.5 v v oh2 output high level ioh = 2ma vcext - 0.4 v v il2 input low level -0.3 0.3 vcext v v ih2 input high level 0.7 vcext vcext + 0.3 v rpu pc pull-up resistor current v = 0 90 280 a c input/output capacitance 1 mhz 10 pf table 34. oscillator signals: xtal1, xtal2 symbol parameter condition min max unit v lh osc1 switching level 0.47 1.20 v v hl osc1 switching level 0.67 1.44 v cx1 input capacitance, xtal1 10 pf cx2 output capacitance, xtal2 10 pf c12 osc1/2 capacitance 5 pf t su start-up time 6 mhz, fundamental 2 ms dl drive level 50 w
91 at43usb351m 3302e?usb?7/04 ac characteristics note: 1. with external 27 ? series resistor. figure 25. full-speed load table 35. usb driver characteristi cs, full speed operation symbol parameter condition min max unit tr rise time c l = 50 pf 4 20 ns tf fall time c l = 50 pf 4 20 ns trfm tr/tf matching 90 110 % zdrv driver output resistance (1) steady state drive 28 44 ? table 36. usb driver characteristi cs, low-speed operation symbol parameter condition min max unit tr rise time cl = 200 - 600 pf 75 300 ns tf fall time cl = 200 - 600 pf 75 300 ns trfm tr/tf matching 80 125 % txd+ txd- r s r s c l c l c l = 50 pf
92 at43usb351m 3302e?usb?7/04 figure 26. low-speed load note: 1. with 6.000 mhz, 100 ppm crystal. txd+ txd- r s r s c l c l c l = 200 pf to 600 pf 3.6v 1.5 k ohm table 37. usb timings, full-speed operation symbol parameter condition min max unit tdrate full speed data rate (1) average bit rate 11.97 12.03 mb/s tframe frame interval (1) 0.9995 1.0005 ms trfi consecutive frame interval jitter (1) no clock adjustment 42 ns trfiadj consecutive fr ame interval jitter (1) with clock adjustment 126 ns tdj1 tdj2 source diff driver jitter to next transition for paired transitions -3.5 -4 3.5 4 ns tfdeop source jitter for differential transition to seo transitions -2 5 ns tjr1 tjr2 receiver data jitter tolerance to next transition for paired transitions -18.5 -9 18.5 9 ns tfeopt source seo interval of eop 160 175 ns tfeopr receiver seo in terval of eop 82 ns tfst width of seo interval during differential transition 14 ns
93 at43usb351m 3302e?usb?7/04 figure 27. differential data jitter figure 28. differential-to-eop transition skew and eop width figure 29. receiver jitter tolerance crossover points paired transitions n*t period + t xjr2 consecutive transitions n*t period + t xjr1 t period differential data lines crossover point extended differential data lines t period diff. data-to- se0 skew n*t period + t deop source eop width: t feopt t leopt receiver eop width: t feopr t leopr t period differential data lines consecutive transitions n*t period + t jr1 consecutive transitions n*t period + t jr1 t jr t jr1 t jr2
94 at43usb351m 3302e?usb?7/04 table 38. usb source timings, low-speed operation symbol parameter condition min max unit tldrate low-speed data rate average bit rate 1.4775 1.5225 mb/s tudj1 tudj2 upstream port source jitter total to next transition for paired transitions -95 -150 95 150 ns tldeop upstream port differential receiver jitter to next transition for paired transitions -40 100 ns tdjr1 tdjr2 upstream port differential receiver jitter to next transition for paired transitions -75 -45 75 45 ns tleopt source seo interv al of eop 1.25 1.50 s tleopr receiver seo interval of eop 670 ns tlst width of seo interval during differential transition 210 ns
95 at43usb351m 3302e?usb?7/04 ordering information program memory ordering code package operation range mask rom AT43USB351M-AC 48 lqfp commercial (0 c to 70 c) package type 48aa 48-lead, 7 x 7 mm body size, low profile plastic quad flat package (lqfp)
96 at43usb351m 3302e?usb?7/04 packaging information 48aa ? lqfp 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 48aa, 48-lead, 7 x 7 mm body size, 1.4 mm body thickness, 0.5 mm lead pitch, low profile plastic quad flat package (lqfp) c 48aa 10/5/2001 pin 1 identifier 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-026, variation bbc. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.08 mm maximum. a 1.60 a1 0.05 0.15 a2 1.35 1.40 1.45 d 8.75 9.00 9.25 d1 6.90 7.00 7.10 note 2 e 8.75 9.00 9.25 e1 6.90 7.00 7.10 note 2 b 0.17 0.27 c 0.09 0.20 l 0.45 0.75 e 0.50 typ
97 at43usb351m 3302e?usb?7/04 errata sheet errata (all date codes): missed watchdog timer reset problem there is a synchronization problem between the watchdog clock and the avr clock. even though the clock inputs to both the watchdog timer and the avr core are generated through the same crystal, the two clock sources are not going through the same pll. the avr is clocked at 12 mhz and the watchdog timer is clocked at 1mhz. the wdr (watchdog reset) instruction is a one-clock-cycle instruction. as such, when a watchdog timer reset occurs due to a wdr, the watchdog timer may miss the reset. this happens frequently if the avr is clocked much faster than the watchdog timer. fix/workaround a workaround is to invoke the wdr repetitively to ensure that the watchdog timer will be able to receive the reset signal. if the avr runs at 12 mhz, the wdr co mmand must be invoked fourteen times back to back. the following is the sample code for resetting and arming the watchdog timer, assuming the avr is running at 12 mhz: asm ( "ldi r16,15\n wdr\n wdr\n wdr\n wdr\n wdr\n wdr\n wdr\n wdr\n wdr\n wdr\n wdr\n wdr\n wdr\n out 0x21,r16 " ); to disarm and disable the watchdog, do the following: asm ( "ldi r16,0x18\nldi r17,0x10\n\n out 0x21,r16\n out 0x21,r17 " ); please note that if the avr runs at 24 mhz, the wdr should be invoked twenty-six times.
98 at43usb351m 3302e?usb?7/04 change log doc. rev. comments 3302e data correction: number of on chip power supplies that generate 3.3v is three (see ?on-chip power supply? on page 18.) 3302d data correction: timeout period data in table 19 on page 51. additions: added an ?errata sheet? on page 97, a ?change log? on page 98 and a ?table of contents? on page i.
i at43usb351m 3302e?usb?7/04 table of contents features............... .............. .............. ............... .............. .............. .......... 1 description .......... .............. .............. ............... .............. .............. .......... 1 pin configuration .................................................................................................. 2 pin assignment..................................................................................................... 3 signal description................................................................................................. 4 architectural overview........ .............. .............. .............. .............. ........ 6 development support ........... ................ ................. ................ ............. 7 the general-purpose regi ster file ........... ................. .............. .......... 8 x-, y- and z- registers ......................................................................................... 9 alu ? arithmetic logic unit.................................................................................. 9 program memory .................................................................................................. 9 sram data memory........................................................................................... 10 i/o memory ......................................................................................................... 15 usb function...................................................................................................... 16 functional description............ ................. ................ .............. ........... 18 on-chip power supply ........................................................................................ 18 i/o pin characteristics ........................................................................................ 18 oscillator and pll .............................................................................................. 18 reset and interrupt handling.............................................................................. 19 reset sources .................................................................................................... 21 power-on reset .................................................................................................. 22 external reset .................................................................................................... 23 watchdog timer reset ....................................................................................... 23 non-usb related interrupt handling.................................................................. 23 external interrupts .............................................................................................. 28 interrupt response time .................................................................................... 28 usb interrupt sources........................................................................................ 30 usb endpoint interrupt sources......................................................................... 31 avr register set ..... ................ ................. ................ .............. ........... 36 status register and stack pointer...................................................................... 36 sleep modes....................................................................................................... 37 timer/counters ........ ................ ................. ................ .............. ........... 38 timer/counter prescaler..................................................................................... 38 8-bit timer/counter0........................................................................................... 39 16-bit timer/counter1......................................................................................... 41 16-bit timer/counter1 operation ........................................................................ 42 watchdog timer ................................................................................................. 50 serial peripheral interface (spi) ......................................................................... 52 analog-to-digital converter ................................................................................. 58
ii at43usb351m 3302e?usb?7/04 i/o-ports........ ................. ................ .............. .............. .............. ........... 65 port a.................................................................................................................. 65 port b.................................................................................................................. 67 port d.................................................................................................................. 69 programming the usb module................ ................ .............. ........... 71 the usb function .............................................................................................. 71 usb registers .................................................................................................... 78 endpoint registers ............................................................................................. 79 suspend and resume ........................................................................................ 87 electrical specification ....... ................ ................. ................ ............. 89 absolute maximum ratings ................................................................................ 89 dc characteristics.............................................................................................. 89 ordering information........... ................ ................. ................ ............. 95 packaging information .......... ................ ................. ................ ........... 96 48aa ? lqfp ..................................................................................................... 96 errata sheet.............. ................ ................. ................ .............. ........... 97 problem .............................................................................................................. 97 fix/workaround .................................................................................................. 97 change log ................ ................. ................ .............. .............. ........... 98 table of contents ................ .............. .............. .............. .............. ......... i
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